• Journal of Power Electronics
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• v.16 no.2
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• pp.769-777
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• 2016

This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage V_GE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.3
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• pp.168-174
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• 2004

This paper describes a new fault location algorithm based on the voltage equation at the relaying point using 6-phase current for untransposed 765㎸ parallel transmission lines. The proposed method uses the voltage and current collected at only the local end. By means of 3-phase circuit analysis theory to compensate the mutual coupling effects between parallel lines, the fault location is derived. The fault distance is determined by solving the 2nd distance equation based on KVL(Kirchhoff's Voltage Law). Extensive simulation results using EMTP(Electromagnatic Transients Program) have verified that the error of the fault location achieved is up to 4.56(%) in untransposed parallel transmission lines.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.11
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• pp.577-582
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• 2004

In this paper, lumped equivalent circuits for a conventional parallel directional coupler are proposed. This equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of parallel-coupled line. By using the derived design formula, we have designed the 3dB and 4.7dB MMIC couplers at the center frequency of 3.4GHz and 5.6GHz respectively. Measurements for the designed MMIC directional couplers show at 4dB and 5.2dB-coupling value at the center frequency of 3.4GHz and 5.6GHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.7
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• pp.465-472
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• 2004

Analog CPPN-based optimal road boundary detection algorithm for autonomous vehicle is proposed. The CPPN is a massively connected analog parallel array processor. In the paper, the dynamic programming which is an efficient algorithm to find the optimal path is implemented with the CPPN algorithm. If the image of road-boundary information is utilized as an inter-cell distance, and goals and start lines are positioned at the top and the bottom of the image, respectively, the optimal path finding algorithm can be exploited for optimal road boundary detection. By virtue of the parallel and analog processing of the CPPN and the optimal solution of the dynamic programming, the proposed road boundary detection algorithm is expected to have very high speed and robust processing if it is implemented into circuits. The proposed road boundary algorithm is described and simulation results are reported.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.45-48
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• 2004

To improve the efficiency characteristics in the resonant converter using the contact-less power supply with the large air-gap and the long primary winding, this paper suggests the three-level series-parallel resonant converter(SPRC). The voltage gain characteristics of the proposed converter have the unit gain in a resonance frequency point of the series and parallel, and input voltage and current in the primary of SPRC are always In phase for the all equivalent load resistance because of the parallel resonant tank of the high impedance. The results are verified on the simulation based on the theoretical analysis and the 4kW experimental prototype.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.1
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• pp.29-36
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• 2009

Realtime tide and storm-surge computations for the Yellow Sea were conducted using the Parallel Finite Element Model. For these computations a high resolution grid system was constructed with a minimum node interval of loom in Gyeonggi Bay. In the modeling, eight main tidal constituents were analyzed and their results agreed well with the observed data. The realtime tide computation with the eight main tidal constituents and the storm-surge simulation for Typhoon Sarah(1959) were also conducted using parallel computing system of MPI-based LINUX clusters. The result showed a good performance in simulating Typhoon Sarah and reducing the computation time.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• Journal of the Korean Solar Energy Society
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• v.37 no.3
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• pp.13-22
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• 2017

Anti-islanding scheme of grid-connected inverter is a key function of standards compliance, since unintentional islanding results in safety hazards, reliability, and many other issues. Therefore, many anti-islanding schemes have been researched, however, most of them have problems, which deteriorate performance of islanding detection under parallel-operation. Therefore, this paper proves the reason of problems and proposes a new anti-islanding scheme that has precise islanding detection under parallel-operation in single-phase and three-phase system. Finally, both simulation and experimental result validate the proposed scheme.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.29-35
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• 2003

This paper presents a fault location algorithm when there are parallel circuits in power system networks. In transmission networks, a fault location method using the distribution factor of fault currents is introduced and in distribution networks a method using direct 3-phase circuit analysis is developed, because the distribution networks are unbalanced. The effect of parallel circuits in fault location is studied in this paper. The effect is important for the range of protecting zones of distance relay in transmission networks and fault location in distribution networks. The result of developed fault location algorithm shows high accuracy in the simulation that using the EMTP.