• Journal of Sensor Science and Technology
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• v.19 no.2
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• pp.99-111
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• 2010

This paper proposes an efficient hardware architecture to estimate disparities between 2D images for generating 3D depth images in a stereo vision system. Stereo matching methods are classified into global and local methods. The local matching method uses the cost functions based on pixel windows such as SAD(sum of absolute difference), SSD(sum of squared difference) and NCC(normalized cross correlation). The NCC-based cost function is less susceptible to differences in noise and lighting condition between left and right images than the subtraction-based functions such as SAD and SSD, and for this reason, the NCC is preferred to the other functions. However, software-based implementations are not adequate for the NCC-based real-time stereo matching, due to its numerous complex operations. Therefore, we propose a fast pipelined hardware architecture suitable for real-time operations of the NCC function. By adopting a block-based box-filtering scheme to perform NCC operations in parallel, the proposed architecture improves processing speed compared with the previous researches. In this architecture, it takes almost the same number of cycles to process all the pixels, irrespective of the window size. Also, the simulation results show that its disparity estimation has low error rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• Journal of Intelligence and Information Systems
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• v.4 no.1
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• pp.133-147
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• 1998

Recently, many researchers have been involved in finding deterministic equations which can accurately predict future event, based on chaotic theory, or fractal theory. The theory says that some events which seem very random but internally deterministic can be accurately predicted by fractal equations. In contrast to the conventional methods, such as AR model, MA, model, or ARIMA model, the fractal equation attempts to discover a deterministic order inherent in time series data set. In discovering deterministic order, researchers have found that neural networks are much more effective than the conventional statistical models. Even though prediction accuracy of the network can be different depending on the topological structure and modification of the algorithms, many researchers asserted that the neural network systems outperforms other systems, because of non-linear behaviour of the network models, mechanisms of massive parallel processing, generalization capability based on adaptive learning. However, recent survey shows that prediction accuracy of the forecasting models can be determined by the model structure and data structures. In the experiments based on actual economic data sets, it was found that the prediction accuracy of the neural network model is similar to the performance level of the conventional forecasting model. Especially, for the data set which is deterministically chaotic, the AR model, a conventional statistical model, was not significantly different from the MLP model, a neural network model. This result shows that the forecasting model. This result shows that the forecasting model a, pp.opriate to a prediction task should be selected based on characteristics of the time series data set. Analysis of the characteristics of the data set was performed by fractal analysis, measurement of Hurst index, and measurement of Lyapunov exponents. As a conclusion, a significant difference was not found in forecasting future events for the time series data which is deterministically chaotic, between a conventional forecasting model and a typical neural network model.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• Journal of Convergence for Information Technology
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• v.10 no.8
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• pp.35-39
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• 2020

DNN error is small compared to the conventional speech recognition system, DNN is difficult to parallel training, often the amount of calculations, and requires a large amount of data obtained. In this paper, we generate a phoneme unit to estimate the GMM parameters with each phoneme model parameters from the GMM to solve the problem efficiently. And it suggests ways to improve performance through clustering for a specific vocabulary to effectively apply them. To this end, using three types of word speech database was to have a DB build vocabulary model, the noise processing to extract feature with Warner filters were used in the speech recognition experiments. Results using the proposed method showed a 97.9% recognition rate in speech recognition. In this paper, additional studies are needed to improve the problems of improved over fitting.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.10
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• pp.851-856
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• 2005

The DNA and protein data of diverse species have been daily discovered and deposited in the public archives according to each established format. Database systems in the public archives provide not only an easy-to-use, flexible interface to the public, but also in silico analysis tools of unidentified sequence data. Of such in silico analysis tools, multiple sequence alignment [1] methods relying on pairwise alignment and Smith-Waterman algorithm [2] enable us to identify unknown DNA, protein sequences or phylogenetic relation among several species. However, in the existing multiple alignment method as the number of sequences increases, the runtime increases exponentially. In order to remedy this problem, we adopted a parallel processing suffix tree algorithm that is able to search for common subsequences at one time without pairwise alignment. Also, the cross-matching subsequences triggering inexact-matching among the searched common subsequences might be produced. So, the cross-matching masking process was suggested in this paper. To identify the function of the clusters generated by suffix tree clustering, BLAST was combined with a clustering tool. Our clustering and annotating tool is summarized as the following steps: (1) construction of suffix tree; (2) masking of cross-matching pairs; (3) clustering of gene sequences and (4) annotating gene clusters by BLAST search. The system was successfully evaluated with 22 gene sequences in the pyrubate pathway of bacteria, clustering 7 clusters and finding out representative common subsequences of each cluster

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1617-1622
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• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.3-8
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• 2006

The next decade promises drastic improvements and additions to global navigation satellite systems (GNSS). Plans for GPS modernization include a civilian code measurement on the L2 frequency and a new L5 signal at 1176.45 MHz. Current speculations indicate that a fully operational constellation with these improvements could be available by 2013. Simultaneously, the Galileo Joint Undertaking is in the development and validation stages of introducing a parallel GNSS called Galileo. Galileo will also transmit freely available satellite navigation signals on three frequencies and is scheduled to be fully operational as early as 2008. In other words, a dual system receiver (e.g., GPS+GALILEO) for general users can access six civil frequencies transmitted by at least fifty eights navigation satellites in space. The advent of GALILEO and the modernization of GPS raise a lot of attention to the study of the compatibility and interoperability of the two systems. A number of performance analyses have been conducted in a global scale with respect to availability, reliability, accuracy and integrity in different simulated scenarios (such as open sky and urban canyons) for the two systems individually and when integrated. Therefore, the scope of this article aims at providing the technical benefits analysis for Taiwan specifically in terms of the performance indices mentioned above in a local scale, especially in typical urban canyon scenarios. The conclusions gained by this study will be applied by the Land Survey Bureau of Taiwanese as the guideline for developing future GNSS tracking facilities and dual GNSS processing module for precise surveying applications in static and kinematic modes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.276-279
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• 2004

Plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiN) is a proven technique for obtaining layers that meet the needs of surface passivation and anti-reflection coating. In addition, the deposition process appears to provoke bulk passivation as well due to diffusion of atomic hydrogen. This bulk passivation is an important advantage of PECVD deposition when compared to the conventional CVD techniques. A further advantage of PECVD is that the process takes place at a relatively low temperature of 300t, keeping the total thermal budget of the cell processing to a minimum. In this work SiN deposition was performed using a horizontal PECVD reactor system consisting of a long horizontal quartz tube that was radiantly heated. Special and long rectangular graphite plates served as both the electrodes to establish the plasma and holders of the wafers. The electrode configuration was designed to provide a uniform plasma environment for each wafer and to ensure the film uniformity. These horizontally oriented graphite electrodes were stacked parallel to one another, side by side, with alternating plates serving as power and ground electrodes for the RF power supply. The plasma was formed in the space between each pair of plates. Also this paper deals with the fabrication of multicrystalline silicon solar cells with PECVD SiN layers combined with high-throughput screen printing and RTP firing. Using this sequence we were able to obtain solar cells with an efficiency of 14% for polished multi crystalline Si wafers of size 125 m square.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.