• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1075-1080
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• 2008

Most modem computers or game consoles are well equipped with powerful graphics processing units(GPUs) to accelerate graphics operations. However, since the graphics engines in these GPUs are specially designed for graphics operations, we could not take advantage of their computing power for more general nongraphic operations. In this paper, we studied the GPUs graphics engine in order to accelerate the image processing capability. Specifically, we implemented a JPEC2000 decoding/encoding framework that involves both OpenMP and GPU. Initial experimental results show that significant speed-up can be achieved by utilizing the GPU power.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• Journal of the Korea Computer Graphics Society
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• v.2 no.1
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• pp.24-30
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• 1996

The ray tracing method, which is one of many photorealistic rendering techniques, requires heavy computational processing to synthesize images. Parallel processing can be used to reduce the computational processing time. A parallel algorithm for the ray tracing has been implemented and executed for various images on transputer systems. In order to develop a scalable parallel algorithm, a processor farming technique has been exploited. Since each image is divided and distributed to each farming processor, the scalability of the parallel system and load balancing are achieved naturally in the proposed algorithm. Efficiency of the parallel algorithm is obtained up to 95% for nine processors. However, the best size of a distributed task is much higher in simple images due to less computational requirement for every pixel. Efficiency degradation is observed for large granularity tasks because of load unbalancing caused by the large task. Overall, transputer systems behave as good scalable parallel processing system with respect to the cost-performance ratio.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.1
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• pp.25-29
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• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.502-504
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• 2010

We propose novel transition rule of cellular automata for image enhancement and sharpening algorithm using it. Transition rule present sequential and parallel behavior. it also satisfy Lyapunov function. This image sharpening was developed and experimented by using a dynamic feature of convergence to fixed points. We can obtain efficiently sharpened image by performing arithmetic operation at the gradual parts of difference of brightness without image information.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.27-33
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• 2005

In this paper, an effective skeleton method is proposed in order to obtain an enhanced digital image of skeleton line. The binary image using the threshold values is applied in the preprocessing stage and then The proposed method is applied to obtain the improved image of skeleton line. We used the existing skeleton methods and SPTA(Shin's Parallel Thinning Algorithm) method for the comparison. The demerits of the existing skeleton methods have a result of noise branch, expansion and contraction. and then we are proposed a SPTA method.

• Journal of the Korea Computer Industry Society
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• v.4 no.10
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• pp.673-684
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• 2003

In order to understand the concepts of image processing with effect, a learning system with an actual practice is necessary. As most image processing learning materials have some inconvenient respects that it is difficult to understand the processing procedure because they simply show the processed results as figures in the contents, and also, a separate practice tool is needed to operate the source codes because they provide the program source codes as a part in the context. In this paper, in order to solve above inconvenient respects, an image processing learning system that be able to improve the learning effects as accomplishing the theory studying and the actual practice in parallel is proposed. As this system is composed on the bases of java, it is independent to the platforms and it is possible to implement on the Web.

• Journal of The Korean Astronomical Society
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• v.51 no.3
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• pp.65-71
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• 2018

The near real-time speckle masking reconstruction technique has been developed to accelerate the processing of solar images to achieve high resolutions for ground-based solar telescopes. However, the reconstruction of solar subimages in such a speckle reconstruction is very time-consuming. We design and implement a new parallel speckle masking reconstruction algorithm based on the Compute Unified Device Architecture (CUDA) on General Purpose Graphics Processing Units (GPGPU). Tests are performed to validate the correctness of our program on NVIDIA GPGPU. Details of several parallel reconstruction steps are presented, and the parallel implementation between various modules shows a significant speed increase compared to the previous serial implementations. In addition, we present a comparison of runtimes across serial programs, the OpenMP-based method, and the new parallel method. The new parallel method shows a clear advantage for large scale data processing, and a speedup of around 9 to 10 is achieved in reconstructing one solar subimage of $256{\times}256pixels$. The speedup performance of the new parallel method exceeds that of OpenMP-based method overall. We conclude that the new parallel method would be of value, and contribute to real-time reconstruction of an entire solar image.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.188-193
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• 2017

In this paper, we propose automatic OpenCL optimization techniques that offer the best performance for image processing programs on any hardware system. Developers should seek a proper way of parallelization and an appropriate work-group size for the architecture of target compute devices to achieve the best performance. However, testing potential devices to find them is both time-consuming and costly. Our techniques automatically set up hardware-optimized parallelization and find a suitable work-group size for the target device. Furthermore, using OpenCL does not always provide better performance in image processing. Hence, we also propose a way to automatically search for a threshold image size to allow image processing programs to decide whether or not to use OpenCL. Our findings demonstrate that out techniques improve the image processing performance significantly.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.23-28
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• 2002

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents the disconnection in the gray-scale image thinning. To extract the skeleton from the image in a real time, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture consists of three blocks, PS(Parallel to Serial) Converter and Stare Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examines the connectivity of the central pixel by searching the data from the PS Converter. The Ridge Checker determines whether the central pixel is on the skeleton or not. The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.