• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.166-168
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• 2002

This paper is concerned with optimal design of BLDC motor using parallel Genetic Algorithm to miminze the motor of weight.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.811-812
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• 2011

• 한국정보통신학회논문지
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• 제14권3호
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• pp.628-636
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• 2010

본 논문에서는 GF($2^m$)상의 표준기저를 사용한 새로운 형태의 VCG에 의한 고속병렬 승산회로를 제안하였다. 승산기의 구성에 앞서, 피승수 다항식과 기약다항식의 승산을 병렬로 수행하는 벡터 코드 생성기(VCG) 기본 셀을 설계하였고, VCG 회로와 승수 다항식의 한 계수와 비트-병렬로 승산하여 결과를 생성하는 부분 승산결과 셀(PPC)를 설계하였다. 제안한 승산기는 VCG와 PPC를 연결하여 고속의 병렬 승산을 수행한다. VCG 기본 셀과 PPC는 각각 1개의 AND 게이트와 1개의 XOR 게이트로 구성된다. 이러한 과정을 확장하여 m에 대한 일반화된 회로의 설계를 보였으며, 간단한 형태의 승산회로 구성의 예를 GF($2^4$)를 통해 보였다. 또한 제시한 승산기는 PSpice 시뮬레이션을 통하여 동작특성을 보였다. 본 논문에서 제안한 승산기는 VCG와 PPC을 반복적으로 연결하여 구성하므로, 차수 m이 매우 큰 유한체상의 두 다항식의 곱셈에서 확장이 용이하며, VLSI에 적합하다.

• Journal of the Korean Data and Information Science Society
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• 제18권2호
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• pp.365-373
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• 2007

Sample size determination plays an important role in designing a bioequivalence trial. Formulae of sample sizes based on Schuirmann's two one-sided tests procedures are given for bioequivalence studies with the $2{\times}2$ crossover design and two-sample parallel design. A practical discussion for the relationship among these formulae is given.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.85-86
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• 2009

• 제어로봇시스템학회논문지
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• 제13권4호
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• pp.320-328
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• 2007

This paper presents a stiffness modeling of a low-DOF parallel robot, which takes into account of elastic deformations of joints and links, A low-DOF parallel robot is defined as a spatial parallel robot which has less than six degrees of freedom. Differently from serial chains in a full 6-DOF parallel robot, some of those in a low-DOF parallel robot may be subject to constraint forces as well as actuation forces. The reaction forces due to actuations and constraints in each serial chain can be determined by making use of the theory of reciprocal screws. It is shown that the stiffness of an F-DOF parallel robot can be modeled such that the moving platform is supported by 6 springs related to the reciprocal screws of actuations (F) and constraints (6-F). A general $6{\times}6$ stiffness matrix is derived, which is the sum of the stiffness matrices of actuations and constraints, The compliance of each spring can be precisely determined by modeling the compliance of joints and links in a serial chain as follows; a link is modeled as an Euler beam and the compliance matrix of rotational or prismatic joint is modeled as a $6{\times}6$ diagonal matrix, where one diagonal element about the rotation axis or along the sliding direction is infinite. By summing joint and link compliance matrices with respect to a reference frame and applying unit reciprocal screw to the resulting compliance matrix of a serial chain, the compliance of a spring is determined by the resulting infinitesimal displacement. In order to illustrate this methodology, the stiffness of a Tricept parallel robot has been analyzed. Finally, a numerical example of the optimal design to maximize stiffness in a specified box-shape workspace is presented.

• 대한기계학회논문집B
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• 제28권3호
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• pp.296-303
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• 2004

The heat and flow characteristics in a single-phase parallel-flow heat exchanger was examined numerically to obtain its optimal shape. A response surface method was introduced to approximately predict its performance with respect to the design parameters over the design domain. The inflow/outflow angle of the working fluid, the location of inlet/outlet, the protruding height of flat tube and the height of header were chosen as a design parameter The evaluation of the relative importance of the design parameters was performed based on a sensitivity analysis. An efficiency index was used as an evaluation characteristics value to simultaneously consider both the heat transfer and the pressure drop. The efficiency index of the optimum model, compared to that of the base model, was increased by 9.3%.

• Journal of information and communication convergence engineering
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• 제11권1호
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2004년도 추계학술대회
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• pp.725-730
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• 2004

This paper has regarded mechanism design of cane-like passive type walking aid for the elderly using 3-RPS parallel manipulator. First, gait patterns of the elderly have been experimented. By means of motion capturing and image processing, we decided loaded forces and places of the cane when the elderly walked with a cane. Using these results we have developed a passive type walking aid. Second, the walking pattern has been simulated using dynamic analysis program, ADAMS and we find out the similarity between the real walking and the simulated walking. Finally after assuring the similarity, with adjusting the new mechanism design to the simulated walking we will decide whether the walking aid is safe and stable when the elderly walks with this cane-like walking aid. This paper will be basis for the development of the mechanism design applying 3-RPS parallel manipulator.

• ETRI Journal
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• 제31권5호
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.