• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.397-403
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• 2014

A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.04a
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• pp.679-684
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• 2000

This paper presents the development of system and program for a Parallel-Typed CNC Machine. The system consists of parallel manipulator, PC (Personal Computer), DMC (DSP Motion Controller), and machining tools. In order to control the manipulator, the program, which is implemented in "c/c++" language, involves inverse/direct kinematics, velocity mapping, Jacobian and etc. A controller computes the kinematic formulation in real-time and generates and motion by the DMC. A monitor, which has access to program and sensory information, displays the status of manipulator.nipulator.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.894-897
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• 1998

A conventional parallel hybrid active filter has an inherent problem of large current ratings of devices used in inverter. In general, this problem has been solved by adjusting turn ratio of a matching transformer. However, making the transformer with high turn ratio may be not available for high power system due to its requirement for high voltage insulation. In this paper, a new configuration is proposed for parallel hybrid active filter. In the proposed hybrid active filter, the active filter is connected to the passive filter inductor in parallel through a matching transformer for the aim of reducing the size of inverter. Through computer simulations, we have shown the outstanding performances of the proposed topology.

• Journal of Communications and Networks
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• v.15 no.3
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• pp.252-257
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• 2013

To alleviate the damage caused by key exposures, Dodis et al. introduced the notion of key-insulated security where secret keys are periodically updated by using a physically insulated helper key. To decrease the risk of helper key exposures, Hanaoka et al. advocated parallel key-insulated mechanism where distinct helpers are independently used in key updates. In this paper, we propose the first parallel key-insulated signature scheme which is provably secure without resorting to the random oracle methodology. Our scheme not only allows frequent key updating, but also does not increase the risk of helper key exposures.

• Review of KIISC
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• v.5 no.2
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• pp.32-48
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• 1995

Our paper describes an Intrusion Detection Parallel System(IDPS) which detects an anomaly activity corresponding to the actions that interaction between near detection events. IDES uses parallel inductive approaches regarding the problem of real-time anomaly behavior detection on rule-based system. This approach uses sequential rule that describes user's behavior and characteristics dependent on time. and that audits user's activities by using rule base as data base to store user's behavior pattern. When user's activity deviates significantly from expected behavior described in rule base. anomaly behaviors are recorded. Observed behavior is flagged as a potential intrusion if it deviates significantly from the expected behavior or if it triggers a rule in the parallel inductive system.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.10a
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• pp.307-314
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• 2000

A parallel condensation algorithm for efficient dynamic analysis of three-dimensional large-scale structures is presented. The algorithm is developed for a user-friendly and cost effective high-performance computing system on a collection of Pentium processors connected via a 100 Mb/s Ethernet LAN. To harness the parallelism in the computing system effectively, a large-scale structure is partitioned into a number of substructures equal to the number of computers in the computing system Then, for reduction in the size of an eigenvalue problem the computations required for static condensation of each substructure is processed concurrently on each slave computer. The performance of th proposed parallel algorithm is demonstrated by applying to dynamic analysis of a three dimensional structure. The results show that how the parallel algorithm facilitates the efficient use of a small number of low-cost personal computers for dynamic analysis of large-scale structures.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.10
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• pp.337-342
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• 2015

We develop a new parallelization method for Sieve of Eratosthenes algorithm, which enhances both computation speed and energy efficiency. A pipeline scheduling is included for better load balancing after proper workload partitioning. They run on multicore CPUs with hybrid parallel programming model which uses both message passing and multithreading computation. Experimental results performed on both small scale clusters and a PC with a mobile processor show significant improvement in execution time and energy consumptions.

• Journal of Power Electronics
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• v.15 no.1
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• pp.116-122
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• 2015

This paper presents a new current sharing control strategy for parallel-connected, synchronised three-phase DC-AC converters employing space vector pulse width modulation (SVPWM) without current sharing reactors. Unlike conventional control methods, the proposed method breaks the paths of the circulating current by dividing the switching cycle evenly between parallel connected equally rated converters. Accordingly, any inter-module reactors or circulating current control will be redundant, leading to reductions in system costs, size, and control algorithm complexity. Each converter in the new scheme employs a synchronous dq current regulator that uses only local information to attain a desired converter current. A stability analysis of the current controller is included together with a simulation of the converter and load current waveforms. Experimental results from a 2.5kVA test rig are included to verify the proposed control method.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1153-1161
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• 2019

A current sharing controller is proposed in this paper for parallel-connected converters. The proposed controller is based on the calculation of the magnitudes of system current space vectors. Good current distribution between parallel converters is achieved with only one Proportional-Integral (PI) compensator. The proposed controller is analyzed and the circulating current impedance is derived for paralleled systems. The performance of the new control strategy is experimentally verified using two parallel connected converters employing Space Vector Pulse Width Modulation (SVPWM) feeding a passive RL load and a 2.2 kW three-phase induction motor load. The obtained test results show a reduction in the current imbalance ratio between the converters in the experimental setup from 53.9% to only 0.2% with the induction motor load.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.9
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• pp.4349-4371
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• 2019

Moldable parallel tasks are widely used in different areas, such as weather forecast, biocomputing, mechanical calculation, and so on. Considering the deadline and the speedup, scheduling moldable parallel tasks becomes a difficulty. Past work majorly focuses on the LA (List Algorithms) or OMA (Optimizing the Middle Algorithms). Different from prior work, our work normalizes execution time and makes all tasks have the same scope in normalized execution time: [0,1], and then according to the normalized execution time, a method is used to search for the reference execution time without considering the deadline of tasks. According to the reference execution time, we get an initial scheduling result based on AFCFS (Adaptive First Comes First Served) policy. Finally, a heuristic approach is used to improve the performance of the initial scheduling result. We call our method HSRET (a Heuristic Scheduling method based on Reference Execution Time). Comparisons to other methods show that HSRET has good performance in AWT (Average Waiting Time), AET (Average Execution Time), and PUT (Percentages of Unfinished Tasks).