• Journal of Korea Multimedia Society
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• v.18 no.10
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• pp.1180-1188
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• 2015

In this paper, a parallel cell contour line extraction algorithm using CUDA, which has no inner contour lines, is proposed. The contour of a cell is very important in a cell image analysis. It could be obtained by a conventional serial contour tracing algorithm or parallel morphology operation. However, the cell image has various damages in acquisition or dyeing process. They could be turn into several inner contours, which make a cell image analysis difficult. The proposed algorithm introduces a min-max coordinates table into each CUDA thread block, and removes the inner contour in parallel. It is 4.1 to 7.6 times faster than a conventional serial contour tracing algorithm.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.95-102
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• 2005

A Parallel Processing model by considering a spatiotemporal parallelism is presented for the training procedure of the MLP neural network. We tried to design the flexible Parallel Processing model by simultaneously applying both of the training-set decomposition for a temporal parallelism and the network decomposition for a spatial parallelism. The analytical Performance evaluation model shows that when the problem size is extremely large, the speedup of each implementation depends, in the extreme, on whether the problem size is pattern-size intensive or pattern-quantify intensive.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.185-190
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• 2006

In this paper, a simple parallel compiler using of Parafrase II is presented. This is a new general method the extracting parallelism in order to parallel processing effectively in nested loop. For this, the source program of Parafrase II parallel compiler is analyzed and implemented. Moreover, this method can be applicable where the dependency relation is both uniform and non-uniform in distance.

• Journal of the Korea Computer Industry Society
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• v.3 no.8
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• pp.981-988
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• 2002

In this paper, a simple parallel compiler of a sequential loop is presented. This is a procedure for the automatic conversion of a sequential loop into a nested parallel DOALL loops at compile time. For this. the source program of Parafrase II parallel compiler is analyzed and a new general method the extracting parallelism in order to parallel processing effectively in nested loop is implemented.

• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.290-298
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• 1994

In this paper we propose parallel sorting algorithm, taking 0( $n^{n}$ log n) time complexity, 0( $n^{x}$ log n) cost (parallel running time * number of processors) and 0( $n^{1-}$x＋ $n^{x}$ )data movement complexity under the ERWW- PRAM model. The methods for solving these problems similar. Parallel algorithm finds pivot for partitioning the data into ordered subsets of approximately equal size by using encording pointers..

• Journal of the Korea Computer Industry Society
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• v.9 no.2
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• pp.63-68
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• 2008

The purpose of a parallel scheduling is to carry out the scheduling with the minimum synchronization overhead and bottleneck under a multiprocessor environment and to perform load balance for a parallel iteration. In this paper, analyse the conventional parallel scheduling methods and drive the problems from each method in order to achive the minimum scheduling overhead and load balance. These problems will go far toward solving the design of effective algorithm.

• International Journal of CAD/CAM
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• v.4 no.1
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• pp.47-53
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• 2004

The subdivision surface is the limit of recursively refined polyhedral mesh. It is quite intuitive that the multi-resolution feature can be utilized to simplify generation of NC (Numerical Control) tool paths for rough machining. In this paper, a new method of parallel NC tool path generation for subdivision surfaces is presented. The basic idea of the method includes two steps: first, extending G-Buffer to a strip buffer (called S-Buffer) by dividing the working area into strips to generate NC tool paths for objects of large size; second, generating NC tool paths by parallel implementation of S-Buffer based on MPI (Message Passing Interface). Moreover, the recursion depth of the surface can be estimated for a user-specified error tolerance, so we substitute the polyhedral mesh for the limit surface during rough machining. Furthermore, we exploit the locality of S-Buffer and develop a dynamic division and load-balanced strategy to effectively parallelize S-Buffer.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1598-1602
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• 2003

The parallel-type mechanism provides more accurate and stiff motion than the serial-type mechanism. However, in case of using the haptic device, the performance of the force reflection can be deteriorated due to the singular points existing in workspace. In this paper, we propose a redundantly actuated parallel 3-DOF haptic device, which is singularity-free in the workspace and has an improved force reflection capability. In addition, we propose a new force distribution algorithm, which can reflect force of both high and low resolution, using two sets of actuator with different size. Redundant actuators are attached to the base frame in order to minimize the inertia of the system. Moreover, a wire and gear reduction system is employed to achieve high force reflection along with soft feeling. We confirm the performance of the force reflection capability throughout simulation.

• Journal of Information Processing Systems
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• v.12 no.1
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• pp.149-168
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• 2016

The Active Appearance Model (AAM) is a class of deformable models, which, in the segmentation process, integrates the priori knowledge on the shape and the texture and deformation of the structures studied. This model in its sequential form is computationally intensive and operates on large data sets. This paper presents another framework to implement the standard version of the AAM model. We suggest a distributed and parallel approach justified by the characteristics of the model and their potentialities. We introduce a schema for the representation of the overall model and we study of operations that can be parallelized. This approach is intended to exploit the benefits build in the area of advanced image processing.