• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.13-16
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• 2005

It would be desirable to have methods for specific problems, which have low communication costs compared to the computation costs, and in specific applications, algorithms need to be developed and mapped onto parallel computer architectures. Main memory access for shared memory system or global communication in message passing system deteriorate the computation speed. In this paper, it is found that the m-step generalization of the block Lanczos method enhances parallel properties by forming m simultaneous search direction vector blocks. QR factorization, which lowers the speed on parallel computers, is not necessary in the m-step block Lanczos method. The m-step method has the minimized synchronization points, which resulted in the minimized global communications compared to the standard methods.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of applied mathematics & informatics
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• v.5 no.2
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• pp.427-432
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• 1998

When an undirected tree T and a vertex ${\gamma}$ in the tree are given the problem to transform T into a rooted tree with ${\gamma}$ as its root is considered. Using Euler tour and prefix sum an optimal algorithm has been developed [2,3]. We will present another parallel algorithm which is optimal also on EREW PRAM. Our approach resuces the given tree step by step by pruning and pointer jumping. That is the tree structure is retained during algorithm processing such that than other tree computations can be carried out in parallel.

• Journal of Power Electronics
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• v.16 no.2
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• pp.769-777
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• 2016

This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage V_GE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.10
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• pp.1057-1065
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• 1990

A parallel processing algorithm for the discrete Kalman filter, which is one of the most commonly used filtering techniques in modern control, signal processing, and communication, is proposed. To decrease the number of computations critical in the Kalman filter, previously proposed parallel algorithms are of the hierarchical structure by distributed processing of measurements, or of the systolic structure to disperse the computational burden. In this paper, a new parallel Kalman filter employing a structure similar to recursive doubling is proposed. Estimated valuse of state variables by the new algorithm converge faster to the true values because the new algorithm can process data twice faster than the conventional Kalman filter. Moreover, it maintains the optimality of the conventional Kalman filter.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.7
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• pp.162-169
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• 2000

In this paper, we develop a parallel inverted pendulum system that has the characteristics of the strongly coupled dynamics of motion by an elastic spring, the time-variant system parameters, and inherent instability, and so on. Hence, it is possible to approximate some kinds of a physical system into this representative system and to apply the various control theories to this system in order to verie their fidelity and efficiency. For this purpose, an experimental system of the parallel inverted pendulum has been implemented, and a control scheme using the eigenstructure assignment for decoupling control is presented in comparison with the conventional LQR optimal control method. Furthermore, this system can be utilized as a testbed to develop and evaluate new control algorithms through various setups. Finally, in this paper, the results of the experiment are compared with those of numerical simulations for validation.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.64-67
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• 1990

A parallel processing algorithm for discrete Kalman filter, which is one of the most commonly used filtering technique in modern control, signal processing, and communication. is proposed. Previously proposed parallel algorithms to decrease the number of computations needed in the Kalman filter are the hierachical structures by distributed processing of measurements, or the systolic structures to disperse the computational burden. In this paper, a new parallel Kalman filter employing a structure similar to recursive doubling is proposed. Estimated values of state variables by the new algorithm converge with two times faster data processing speed than that of the conventional Kalman filter. Moreover it maintains the optimality of the conventional Kalman filter.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 1998.10a
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• pp.362-369
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• 1998

The computational environment in which engineers perform their designs has been rapidly evolved from coarse serial machines to massively parallel machines. Although the recent development of high-performance computers are available for a number of years, only limited successful applications of the new computational environments in computational structural engineering field has been reported due to its limited availability and large cost associated with high-performance computing. As a new computational model for high-performance engineering computing without cost and availability problems, parallel structural analysis models for large scale structures on a network of personal computers (PCs) are presented in this paper. In structural analysis solving routine for the linear system of equations is the most time consuming part. Thus, the focus is on the development of efficient preconditioned conjugate gradient (PCG) solvers on the proposed computational model. Two parallel PCG solvers, PPCG-I and PPCG-II, are developed and applied to analysis of large scale space truss structures.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.29-35
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• 2003

This paper presents a fault location algorithm when there are parallel circuits in power system networks. In transmission networks, a fault location method using the distribution factor of fault currents is introduced and in distribution networks a method using direct 3-phase circuit analysis is developed, because the distribution networks are unbalanced. The effect of parallel circuits in fault location is studied in this paper. The effect is important for the range of protecting zones of distance relay in transmission networks and fault location in distribution networks. The result of developed fault location algorithm shows high accuracy in the simulation that using the EMTP.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.183-185
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• 1988

Some efficient methods for solving the equations over GF($2^m$) are proposed in this paper. Using these algorithms, parallel decoder for a triple-error-correcting(31, 16) BCH code is implemented. By incorporating with ROM and PAL which are inserted in a decoder, the complex logic circuits can be substantially reduced and therefore a high speed decoder can be constructed.