• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.59-64
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• 2014

Transfer is the critical issue of producing high-quality and scalable graphene electronic devices. However, conventional transfer processes require the removal of an underlying metal layer by wet etching process, which induces significant economic and environmental problems. We propose the etching-free mechanical releasing of graphene using polymer adhesives. A fracture mechanics approach was introduced to understand the releasing mechanism and ensure highyield process. It is shown that the thickness of adhesive and target substrate affect the transferability of graphene. Based on experimental and fracture mechanics simulation results, we further observed that compliant adhesives can reduce the adhesive stress during the transfer, which also enhances the success probability of graphene transfer.

• Transactions of Materials Processing
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• v.13 no.1
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• pp.65-71
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• 2004

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole qualify is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene terephthalate) one. In this paper we found the correlation between hole quality and process condition such as PET thickness and ceramic thickness. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.19-26
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• 2014

Through Silicon Via (TSV) technology is the shortest interconnection technology which is compared with conventional wire bonding interconnection technology. Recently, this technology has been also noticed for the miniaturization of electronic devices, multi-functional and high performance. The short interconnection length of TSV achieve can implement a high density and power efficiency. Among the TSV technology, TSV filling process is important technology because the cost of TSV technology is depended on the filling process time and reliability. Various filling methods have been developed like as Cu electroplating method, molten solder insert method and Ti/W deposition method. In this paper, various TSV filling methods were introduced and each filling materials were discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.239-242
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• 2003

Optical module package is a hermetic metal-ceramic package for carrying optical IC. In case of LD(laser diode) module, window is used for both the path of optical signal and hermetic sealing of package. So, window has the metallization pattern on the surface for brazing process with package wall. In this study, several method were investigated for metallization. Thin film, thick film and mixed method were used for fabrication of metallization pattern. After brazing process, hermeticity and adhesion strength were tested for characterization of metallization pattern.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.169-173
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• 2003

We demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon) printed circuit board (PCB). The copper lines were formed with $100\;{\mu}m$ width and $18\;{\mu}m$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of $100-200\;{\mu}m$. The DFRs of $15\;{\mu}m$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100^{\circ}C\;to\;150^{\circ}C$ and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63 cm/s. And the smallest size of indium solder bump was diameter of $50\;{\mu}m$ with pitch of $100\;{\mu}m$.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.11-17
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• 2001

The design and manufacture of injection molded polymeric parts with desired properties is a costly process dominated by empiricism, including the repeated modification of actual tooling. This paper presents an expert design evaluation system which can predict the mechanical performance of a molded product and diagnose the design before the actual mold is machined. The knowledge-based system synergistically combines a rule-based expert system with CAE programs. Heuristic knowledge of injection molding is formalized as rules of an expert consultation system. The expert system interprets the analytical results of the process simulation, predicts the performance, evaluates the design and generates recommendations for optimal design alternatives.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.25-29
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• 2002

Single ion exchange process was used, and the ion exchange behavior and mechanical properties were investigated in substrate glass for flat panel display. In order to study the effects of ion exchange, ion exchange behavior with ion penetration depth, amount of ion exchange, density and thermal expansion was measured according to the time and temperature. The mechanical properties were evaluated by the three point bending test and curvature change, and then the fracture patterns were investigated by optical microscope.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.33-37
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified fer other bonding methods such as ACF.