• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.177-193
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• 2000

• 월간포장계
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• 통권213호
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• pp.72-79
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• 2011

• 월간포장계
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• 통권309호
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• pp.78-85
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• 2019

• 월간포장계
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• 통권356호
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• pp.88-93
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• 2022

• 마이크로전자및패키징학회지
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• 제26권4호
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• pp.7-13
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• 2019

Power module is getting attention from electronic industries such as solar cell, battery and electric vehicles. Transient liquid phase (TLP) boding, sintering with Ag and Cu powders and wire bonding are applied to power module packaging. Sintering is a popular process but it has some disadvantages such as high cost, complex procedures and long bonding time. Meanwhile, TLP bonding has lower bonding temperature, cost effectiveness and less porosity. However, it also needs to improve ductility of the intermetallic compounds (IMCs) at the joint. Wire boding is also an important interconnection process between semiconductor chip and metal lead for direct bonded copper (DBC). In this study, TLP bonding using Sn-based solders and wire bonding process for power electronics packaging are described.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• 제어로봇시스템학회논문지
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• 제16권2호
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• pp.172-176
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• 2010

Recently, LCD (Liquid Crystal Display) requires various technical challenges; high definition, high quality, big size, and low price. These demands more pixels in the fixed area of the LCD and very fine lead pitch of the driving IC which controls the pixels. Therefore, a new packaging technology is needed to meet such technical requirement. NCP (Non Conductive Paste) is one of the new packaging methods and has excellent characteristics to overcome the problems of the ACF (Anisotropic Conductive Film). In this paper, we analyzed the process of the NCP for COF (Chip on FPCB) and proposed the key design parameters of the NCP process. Through a series of experiments, we obtained the stable values of the design parameters for successful NCP process.

• 월간포장계
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• 통권86호
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• pp.103-108
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• 2000

• 월간포장계
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• 통권252호
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• pp.88-91
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• 2014

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.77-95
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• 2000