• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.39-44
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• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.05a
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• pp.12.2-12.2
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• 2007

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2001.01a
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• pp.224-229
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• 2001

When a semiconductor package is assembled, various materials such as die attach adhesive, lead frame, EMC (Epoxy Molding Compound), and gold wire are used. For better preconditioning performance, the combination between the packaging materials by studying the compatibility of their properties as well as superior packaging material selection is important. But it is not an easy task to find proper packaging material sets, since a variety of factors like package design, substrate design, substrate size, substrate treatment, die size, die thickness, die passivation, and customer requirements should be considered. This research applies case-based reasoning(CBR) technique to solve this problem, utilizing prior cases that have been experienced. Our particular interests lie in building decision support model to aid the selection of proper die attach adhesive. The preliminary results show that this approach is promising.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.262-263
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• 2007

In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

• Journal of the Korean institute of surface engineering
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• v.56 no.1
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• pp.77-83
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• 2023

The reliability of leadframe-based semiconductor package depends on the adhesion between metal and epoxy molding compound (EMC). In this study, the Ag surface was electrochemically treated in a solution containing silanes in order to improve the adhesion between Ag and epoxy substrate. After electrochemical treatment, the thin silane layer was deposited on the Ag surface, whereby the peel strength between Ag and epoxy substrate was clearly improved. The improvement of peel strength depended on the functional group of silane, implying the chemical linkage between Ag and epoxy.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.75-81
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• 2015

In this paper, numerical analysis by finite element method and parameter design by the Taguchi method were used to reduce warpage of a two passive components embedded double side substrate for PoP(Package on Package). The effect of thickness of circuit layers (L1, L2) and thickness of solder resist (SR_top, SR_BTM) were analyzed with 4 variations and 3 levels(minimum, average and maximum thickness) to find optimized thickness conditions. Also, paste effect of solder resist on unit area of top surface was analyzed. Finally, experiments was carried out to prove numerical analysis and the Taguchi method. Based on the numerical and experimental results, it was known that circuit layer in ball side of substrate was the most severe determining deviation for reducing warpage. Buried circuit layer in chip side, solder resist and were insignificant effects on warpage relatively. However, warpage decreased as circuit layer in ball side thickness increased but effect of solder resist and circuit layer in chip side thickness were conversely.

• Journal of Mechanical Science and Technology
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• v.18 no.9
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• pp.1572-1581
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• 2004

The purposes of the paper are to apply the axiomatic design methodology to the design of PBGA package with polyimide coating under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by stress analysis. The analysis model is a 256-pin perimeter Plastic Ball Grid Array (PBGA) package with the polyimide coating surrounding chip and above surface of BT-substrate. The polyimide coating is suggested to depress the maximum stresses occurred on the stress concentration positions. The axiomatic design methodology is proved to be useful to find the more reliable design conditions for PBGA package. Finally, the optimal values of design variables to depress the stress in the PBGA package are obtained.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.9-25
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• 2001

Fairchild has been developing a new class IPM called SPM consisting of dramatic Packaging technology to achieve the lowest cost rind better performance for low power home appliances and industrial AC drive applications. The first Fairchild SPM development with IGBT 600V/15A for washing machine application started in 1999 and was completed successfully. Fairchild SPMs are going to be the best solution for low power inverter-driven AC drive system after 2001. The new SPM Packages like SPM ∥ and SPIM for the next generation IPM with the highest competitiveness (cost & performance) shall be continuouslly developed.