• International Journal of Control, Automation, and Systems
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• 제4권5호
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• Journal of Advanced Marine Engineering and Technology
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• 제35권2호
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• pp.288-294
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• 2011

본 논문에서는 FPGA기반의 SoC보드(Xilinx Virtex-4 ML401 EVM)를 이용한 전력인버터제어시스템을 설계하였다. 선박에 전력시스템을 적용하기 위해서 선박의 최신 통신 프로토콜인 NMEA 2000 표준 프로토콜을 적용하였으며 전력 시스템의 성능을 평가하기 위한 PC기반의 모니터링 프로그램을 제작하였다. 전력 제어시스템은 FPGA기반의 임베디드 SoC보드상에서 이중프로세서(Dualprocessor)형태로 설계하였으며 이중프로세서를 적용함으로써 실시간 제어 감시가 가능하다. 이중프로세서 중 하나는 전력 제어를 위한 PWM신호생성 및 전력 회로내의 주요 전력 파라미터를 센싱 하는 제어용 프로세서로 동작하며(Control processor) 다른 프로세서는 제어프로세서의 각종 전력 센서 파라미터와 제어 파라미터들을 이중포트 램(Dual Port RAM)을 이용하여 정보를 공유하고 외부 NMEA 2000프로토콜 기반의 모니터링 장치와 네트워크 기반의 통신을 수행하는 통신용 프로세서(Communication processor)로 구성된다. 본 논문에서 제작한 전력 제어시스템은 선박내의 분산발전,송배전 및 전압 레귤레이션 시스템에 적용 될 수 있다.

• 전기전자학회논문지
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• 제12권4호
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• pp.239-245
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• 2008

In this paper, a dc-dc power converter scheme with the FPGA based technology is proposed to apply for solar power system which has many features such as the good waveform, high efficiency, low switching losses, and low acoustic noises. The circuit configuration is designed by the conventional control type converter circuit using the isolated dc power supply. This new scheme can be more widely used for industrial power conversion system and many other purposes. Also, I proposed an efficient photovoltaic power interface circuit incorporated with a FPGA based DC-DC converter and a sine-pwm control method full-bridge inverter. The FPGA based DC-DC converter operates at high switching frequency to make the output current a sine wave, whereas the full-bridge inverter operates at low switching frequency which is determined by the ac frequency. As a result, we can get a 1.72% low THD in present state using linear control method. Moreover, we can use stepping control method, we can obtain the switching losses by Sp measured as 0.53W. This paper presents the design of a single-phase photovoltaic inverter model and the simulation of its performance.

• 한국산학기술학회논문지
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• 제7권5호
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• pp.963-969
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• 2006

본 연구에서는 태양광 발전시스템의 최대전력추종을 위해 퍼지 이론을 도입한 디지털 퍼지제어기를 설계하였다. 그리고 퍼지제어기의 디지털 설계를 위해 소용량 태양광 발전시스템의 각 부분을 구성하고 이를 적용하여 기존의 제어기와 비교 실험하였다. FPGA로 구현된 제어기는 기존의 마이크로프로세서로 구현된 제어기에 비해 일사량 변화에도 출력전압의 변동이 적은 안정적인 동작특성을 보였다.

• 전기전자학회논문지
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• 제26권1호
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• pp.43-49
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• 2022

본 논문은 전동기의 저속 영역 운전의 센서리스 기법으로 적합한 고조파 주입 센서리스 제어기법에서 사인파, 삼각파 및 사각파를 주입하여 인가 전압 파형에 따른 센서리스 성능을 비교한다. 본 연구는 영구자석 전동기의 센서리스 기법에 관한 것이다. 1kHz 주파수를 갖는 여러 모양의 파형을 주입하여, 각 파형에 대한 추정된 각도의 오차량을 비교 분석한다. 실험은 HILS(hardware in the loop simulation) 시스템을 이용하였으며, Hardware는 제어보드이며 실시간 시뮬레이터에는 Simulik로 구현된 인버터와 전동기의 모델이 위치한다. 제어 알고리즘은 FPGA 제어보드로 구현하였으며, 이는 10kHz 주파수의 PWM 인터럽트 서비스 루틴, 고조파 주입 및 위치 검출 센서리스 알고리즘 등을 포함한다. HILS 실험을 통해 사인파, 삼각파 및 사각파 고조파 주입시 센서리스 제어 성능을 비교한다.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• 제어로봇시스템학회논문지
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• 제9권5호
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• pp.354-360
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• 2003

For the convenient use of high performance microprocessor in motor control, peripheral devices are needed for converting its control signals to compatible ones for motor drive. Customized devices are not plentiful far these purposes and their functions do not usually satisfied designers specification. The designers used to implement these functions on FPGA or CPLD using hardware description language. Then, in this case unessential programs are needed for control the peripherals. In this paper, a unified device model that links peripheral devices, including especially the pulse width modulation controller and the quadrature encoder interface device, to an interrupt controller is proposed. Advanced functions of peripherals could be achieved by this model and unessential programs can be simplified. Block diagrams and flowcharts are presented to illustrate the advanced functions. This unified device was designed using VHDL. The simulation results were presented to demonstrate the effectiveness of the proposed scheme.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1540-1551
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• 2015

The detection of position and speed in BLDC motors without using position sensors has meant many efforts for the last decades. The aim of this paper is to develop a sensorless technique for detecting the position and speed of BLDC motors, and to overcome the drawbacks of position sensor-based methods by improving the performance of traditional approaches oriented to motor phase voltage sensing. The position and speed information is obtained by computing the derivative of the terminal phase voltages regarding to a virtual neutral point. For starting-up the motor and implementing the algorithms of the detection technique, a FPGA board with a real-time processor is used. Also, a versatile hardware has been developed for driving BLDC motors through pulse width modulation (PWM) signals. Delta and wye winding motors have been considered for evaluating the performance of the designed hardware and software, and tests with and without load are performed. Experimental results for validating the detection technique were attained in the range 5-1500 rpm and 5-150 rpm under no-load and full-load conditions, respectively. Specifically, speed and position square errors lower than 3 rpm and between 10º-30º were obtained without load. In addition, the speed and position errors after full-load tests were around 1 rpm and between 10º-15º, respectively. These results provide the evidence that the developed technique allows to detect the position and speed of BLDC motors with low accuracy errors at starting-up and over a wide speed range, and reduce the influence of noise in position sensing, which suggest that it can be satisfactorily used as a reliable alternative to position sensors in precision applications.

• Journal of Power Electronics
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• 제10권2호
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• pp.132-137
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• 2010

Interleaving techniques are widely used to reduce input/output ripples and to increase the power capacity of boost converters operating in critical conduction mode. Two types of phase-shift control schemes are studied in this paper, the turn-on time shifting method and the turn-off time shifting method. It is found that although the turn-off time shifting method exhibits better performance, it suffers from sub-harmonic oscillations at high input voltages. To solve this problem, an intensive quantitative analysis of the sub-harmonic oscillation phenomenon is made in this paper. Based upon that, a novel modified turn off time shifting control scheme for interleaved boost converters operating in critical conduction mode is proposed. An important advantage of this scheme is that both the master phase and the slave phase can operate stably in critical conduction mode without any oscillations in the full input voltage range. This method is implemented with a FPGA based digital PWM control platform, and tests were carried out on a two-phase interleaved boost PFC converter prototype. Experimental results demonstrated the feasibility and performance of the proposed phase-shift control scheme.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.461-466
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• 2003

This paper presents the speed control of the surface-mounted permanent-magnet synchronous motors (SMPMSM) for the elevator drive. The elevator motor needs to be a compact and slim type. Essentially, the proposed scheme uses a vector control algorithm for a speed and torque control. This system is implemented using a high speed 32-bit DSP (TMS320C31-50), a high-integrated logic device FPGA (EPF10K10-Tl144-3) to design compactly and Inexpensively The proposed scheme is verified through digital simulation and experiments for a three-phase 13.3kW SMPMSM as a MRL(MachineRoomless) elevator motor ill the laboratory. Finally, experiment of the test tower was performed with a 48kW PWM converter-inverter system for a high- speed elevator .