• 제목/요약/키워드: PSPICE

검색결과 365건 처리시간 0.028초

전계방전형 외부전극 형광램프의 모델과 구동특성 (A Study on the Impedance Model and Driving Performance for the Electrical Discharge Type External Electrode Fluorescent Lamp)

  • 김철진;유병규
    • 전기학회논문지
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    • 제57권7호
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    • pp.1181-1186
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    • 2008
  • A impedance model simulating the electrical characteristics of the External Electrode fluorescent lamp operated at high frequency is proposed. The model is constructed from a two parameter equation which is derived based on a set of two measurements. This is a readily constructed and computer simulator oriented model which is suitable for a preliminary design of electronic ballasts. Simulated and experimental results are used to verify the analytical discussions, and moreover, an electronic ballast design example using the proposed model is presented to further demonstrate its application.

An Improved Distributed Equivalent Circuit Modeling for RF Components by Real-Coefficient AFS Technique

  • Kim, Koon-Tae;Ko, Jae-Hyeong;Paek, Hyun;Kahng, Sung-Tek;Kim, Hyeong-Seok
    • Journal of Electrical Engineering and Technology
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    • 제6권3호
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    • pp.408-413
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    • 2011
  • In this paper, a real-coefficient approach to Adaptive Frequency Sampling (AFS) technique is developed for efficient equivalent circuit modeling of RF components. This proposed method is advantageous than the vector fitting technique and the conventional AFS method in terms of fewer samples leading to a lower order of a rational function on a given data and to a direct conversion to an equivalent circuit for PSPICE(Personal Simulation Program with Integrated Circuit Emphsis) simulation, respectively. To validate the proposed method, the distributed equivalent circuit of a presented multi-layered RF low-pass filter is obtained using the proposed real-coefficient AFS, and then comparisons with EM simulation and circuit simulation for the device under consideration are achieved.

턴 온 상태를 고려한 NPT IGBT의 과도 특성 모델링 (Modeling transient characteristics of NPT IGBT including trun-on condition)

  • 류세환;이용국;안형근;한득영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.327-330
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    • 2003
  • In this work, current-voltage characteristics with time of NPT(Non-PunchThrough) IGBT is proposed during turn-on and turn-off by using analytical method. From the results, power loss at turn-off dominates the total electrical loss with respect to that at turn-on. The results have been compared with those of PSPICE and show the identical trend of power loss with each other.

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LED 드라이버 시뮬레이션을 위한 드라이버 IC 모델링 기법 (Driver IC Modeling Technique for LED Driver Simulation)

  • 이윤재;최범호;유윤섭
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2010년도 하계학술대회 논문집
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    • pp.222-223
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    • 2010
  • TOP245P driver IC modeling technique are proposed for the LED Driver design. Analog behavioral model of TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The averaged-model and switching-model is applied to the LED driver simulation. The simulation results by the proposed TOP245P IC modeling technique are in good agreement with that in the data sheet and an experiment data.

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High-Speed BiCMOS Comparator

  • Jirawath, Parnklang;Wanchana, Thongtungsai
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.510-510
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    • 2000
  • This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

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OTA-C Realization of Electronically Tunable Current-Mode Biquadratic filters

  • Tangsrirat, Worapong;Unhavanich, Sumalee;Dumawipata, Teerasilapa;Surakampontorn, Wanlop
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.454-454
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    • 2000
  • An active-C biquadratic filter structure is proposed which consists of only seven OTAs and two grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass and highpass transfer functions without changing circuit topology. This technique provides many advantages which include low passive and active sensitivities and, moreover, its Q-factor is electronically tunable and separately from the tuning of the natural angular frequency ${\omega}_o$. PSPICE simulation results are obtained that confirm the theoretical analysis.

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A high frequency CMOS precision full-wave rectifier

  • Riewruja, V.;Wangwiwattana, C.;Guntapong, R.;Chaikla, A.;Linthong, A.
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.514-514
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    • 2000
  • In this article, the realization of a precision full-wave rectifier circuit for analog signal processing, which operates throughout in the current domain, is presented. The circuit makes use of a MOS class B/AB configuration, and provides a wide dynamic range and wide-band capability. The rectifier has a simple circuit configuration and is suitable for implementing in CMOS integrated circuit form as versatile building block. The characteristic of the circuit exhibits a low distortion en the output signal at low level input signal. PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

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Domino CMOS NOR-NOR Array Logic의 Testable Design에 관한 연구 (A study on the Testable Design of Domino CMOS NOR-NOR Array Logic)

  • 이중호;조상복
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.574-578
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    • 1988
  • This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.

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저전압 스트레스를 갖는 AT 포워드 다중 공진형 컨버터 (AT forward MRC with a low voltage stress)

  • 황치면;김희준;김창선;김영태
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 F
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    • pp.2042-2044
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    • 1998
  • In this paper, we proposed the alternated forward multi-resonant converter. It can reduce the voltage stress due to the operation of two multi resonant switches and also provides a high frequency applications. The proposed circuit is verified through the PSpice simulation and the 50W experimental set with 2MHz maximum frequency. The measured voltage stress is up to 170V of 2.9 times the input voltage and the efficiency is about 81.66% at low line.

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Static Induction Thyristor의 시동특성해석 (The Simplified Model For Switching Transient Characteristics Analysis Of SI Thyristor)

  • 이민근;박만수;고광철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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    • pp.1219-1220
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    • 2006
  • 본 연구의 목적은 Pspice를 이용하여 SI Thyristor의 구조적인 특징과 스위칭 동작을 설명하면서도 비교적 간략화된 등가 모델을 개발하는 것에 있다. 이러한 목표로 등가모델은 SI Thyristor의 구조적 형태에 기반을 두어 BJT 소자를 이용한다. 또 게이트 구조와 스위칭 매커니즘을 고려한 MOSFET, Steady state Turn on 상태에서 dominant 모델인 PIN Diode로 구성되어 있다. 개발된 등가모델을 스너버회로와 함께 스위칭 과도응답을 시뮬레이션하였으며 그 결과는 실제 실험결과와 비교하여 검증하였다. 비교적 간단하게 고안된 회로를 통해 Turn On/Off 동작에서 스위칭 특성을 예측할 수 있으므로 펄스파워용 스위치로서 SI Thyristor의 시동특성을 해석하는 데 본 등가모델을 활용할 수 있을 것으로 전망한다.

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