• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.113-118
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• 2010

In This Paper, at the PSPICE model is presented by Piezoelectric Transformer and CCFL and equivalent circuit of fluorescent light. Highly effective fluorescent light release for next generation is developed for 35W supremacy model three wave length T5 fluorescent lamps. Lighting a candle experiment of T5 fluorescent lamps is carried out by employing Piezoelectric Transformer power-factor improvement circuit and inverter. PLL method is used for supplying a correct frequency of Piezoelectric Transformer operating.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.3
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• pp.122-129
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• 2001

Exact simulation of conducted EMI in switched mode power supplies is proposed. In order to achieve exact simulation, PSPICE active component ABM model and modified transformer model are proposed. Each model parameter is extracted from measurements and data-books. PSPICE simulation results with high frequency PCB pattern model are accordant with EMI measurements for a 50[W] isolated flyback converter. EMI relations of each component and EMI patterns are analyzed.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2161-2163
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• 1999

Generally, ZnO varistors have dynamic characteristics that the cut-off voltage increases as the time to crest of the varistor current decreases. Dynamic characteristics of ZnO varistor are the most important factor in region of the steep front discharge current particularly. Also, V-I characteristics of ZnO varistor have hysterisis loop in time domain and frequency dependency. This paper deals with ZnO varistor numerical equation and modeling method which takes the behavior of varying clamping voltage into consideration during the time to crest, in range of $1{\mu}m{\sim}50{\mu}m$, of impulse current applied to a ZnO varistor. The simulated results by the proposed model are compared with experimental results for each of the impulse current.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1223-1224
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• 2006

본 논문에서는 Half Bridge Series Resonant Inverter를 이용한 유도가열 시스템 설계를 하고 제작하여 구현하였다. 이러한 유도가열 시스템의 제작을 위해서는 공진탱크와 매칭 트랜스포머의 설계가 필수적이다. 따라서 이런 설계를 위해 PSpice 를 이용하여 공진탱크의 입력 임피던스 Bode Plot 을 그려 분석하고 이를 바탕으로 탱크회로를 설계 하였다. 매핑 트랜스포머의 설계는 출력 Power 와 1,2 차 회로 조건에 의해 설계 되어졌다. 이렇게 설계한 유도가열 시스템을 Pspice 를 이용해서 Simulation 함으로써 주파수에따른 출력 Power 의 변화를 볼수 있었으며, 유도가열 시스템을 실제 제작하여 구현함으로써 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.12
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• pp.686-691
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• 1999

In a switching power supply, the high frequency switching makes the passive components small, but the losses and the stresses of switches are increased by the switching frequency. Therefore, zero crossing technology using resonant is used to improve defect in high switching. In generally, zero crossing switching consists of Zero Current Switching(ZCS) and Zero Voltage Switching(ZVS). This paper proposes A Buck ZC-ZVS Converter with Reduced Conduction Losses. Comparing with a conventional Buck ZC-ZVS Converter, the proposed converter operates with the smaller rated power. This is achieved by changing the auxiliary switch position, which reduces its rating power. Simulation results using Pspice program about test circuit with rated 160W(30V, 5.3A) at 30kHz and experiment result under same condition were described in the paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.278-281
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• 1999

In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.

• Journal of Power Electronics
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• v.11 no.5
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• pp.677-687
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• 2011

In this paper a cycloconverter-type high frequency transformer link inverter with a reduced switch count is analyzed and designed. The proposed topology consists of an H-bridge inverter at the transformer's primary side and a cycloconverter with three bidirectional switches at the secondary. All of the switches of the cycloconverter operate in non-resonant zero voltage and zero current switching modes. To overcome a high voltage surge problem resulting from the transformer leakage inductance, phase angle control based on natural commutation is employed. The effectiveness of the proposed inverter is verified by constructing s 750W prototype. Experimentally, the inverter is able to supply a near sinusoidal output voltage with a total harmonic distortion of less than 1%. For comparison, a PSpice simulation of the inverter is also carried out. It was found that the experimental results are in very close agreement with the simulation.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.1
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• pp.80-86
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• 2002

A neural network structure which is able to perform the operations of analog addition and linear equation is proposed. The network employs Hopfkeld's model of a neuron with the connection elements specified on the basis of an analysis of the energy function. The analog addition network and linear equation network are designed by using Hopfield's A/D converter and linear programming respectively. Simulation using Pspice has shown convergence predominently to the correct global minima.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1683-1684
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• 2006

본 논문에서는 Half Bridge Series Resonant Inverter 를 이용한 유도가열 시스템 설계를 하고 제작하여 구현하였다. 이러한 유도가열 시스템의 제작을 위해서는 공진탱크와 매칭 트랜스포머의 설계가 필수적이다. 따라서 이런 설계를 위해 PSpice를 이용하여 공진탱크의 입력 임피던스 Bode Plot 을 그려 분석하고 이를 바탕으로 탱크회로를 설계 하였다. 매칭 트랜스포머의 설계는 출력 Power 와 1,2 차 회로 조건에 의해 설계 되어졌다. 이렇게 설계한 유도가열 시스템을 PSpice를 이용해서 Simulation 함으로써 주파수에 따른 출력 Power 의 변화를 볼 수 있었으며, 유도가열 시스템을 실제 제작하여 구현함으로써 확인하였다.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.326-328
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• 1996

The 10kW or 1MW model of a photovoltaic array written in PSPICE is presented in this paper. A problem with this large scale centralized photovoltaic system is the decrease of power due to the resistance of cable connecting individual subarray with inverter. In this paper, we analyzed the relationship between the resistance of cable and subarray output power of 1MW photovoltaic system by the PSPICE modeling. As a result of simulation, we can proved that photovoltaic array output power is limitted by the resistance of cable.