• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.31-40
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• 2004

In this paper, we analyze mathematically the performance of the gated service scheduling in the Interleaved Polling with Adaptive Cycle Time(IPACT) was proposed to control upstream traffic for Gigabit Ethernet-PONs. In the analysis, we model EPON MAC protocol as a polling system and use mean value analysis. We divide arrival rate λ into three regions and analyze each region accordingly In the first region in which λ value is very small, there are very few ONUs' data to be transmitted. In the second region in which λ has reasonably large value, ONUs have enough data for continuous transmission. In the third region, ONUs' buffers are always saturated with data since λ value is very large. We obtain average packet delay, average Queue size, average cycle time of the gated service. We compare analysis results with simulation to verify the accuracy of the mathematical analysis. Simulation requires much time and effort to evaluate the performance of EPONs. On the other hand, mathematical analysis can be widely used in the design of EPON systems because system designers can obtain various performance results rapidly. We can design appropriate EPON systems for varioustraffic property by adjusting control parameters.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.