• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.599-607
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• 2004

In this paper, using phase locked loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation fur modulation signal whose frequency covers from outside to inside of the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and of blocking the intereference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design. In addition, the novel measurement method of the wideband FM modulation index is suggested verified With the suggest measurement, it can be successfully shown the designed circuit has the expected frequency deviation.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.189-192
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• 1999

The switched reluctance drive system is known to provide a good adjustable speed and torque characteristics. However, acoustic noise and higher torque ripple are drawbacks. These drawbacks show the fact that SRM drive is not operated with mmf current specified for dwell angle and input voltage. Reducing torque ripple and having precise speed control, PLL technique is adopted. The PLL system in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. A TMS320F240 based on the DSP is used to realizing this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.200-202
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• 2005

In this paper, improved rotor position estimation for position sensorless control system of the SRM (Switched Reluctance Motor) is presented. For more accurate rotor position estimation, the PLL (Phase Locked Loop) based position interpolation is adapted. In the current-flux-rotor position lookup table based rotor position estimation, the inherent current and flux-linkage ripple can cause the position estimation error. Instead of the conventional low-pass filter, the PLL based position interpolation technique is used for the better dynamic performance. The developed rotor position estimation scheme is realized using TMS320F2812 digital signal processor and prototype 1-hp SRM.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.7
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• pp.107-112
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• 2005

RThis paper presents a high voltage capacitor charging power supply(CCPS) using a series resonant inverter. The CCPS adopted a 45[kHz] IGBT series resonant inverter using PLL control and a high-efficiency, high-voltage transformer. The performance test of the CCPS was carried out with a 14 nF load capacitor at 100[kV] output voltage and 200[Hz] repetition rate. Peak power rate of 18.75[kJ/sec] and charging time of 4.5[mS].

• Macromolecular Research
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• v.14 no.3
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• pp.348-353
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• 2006

For enhancing the gene delivery efficiency of polyplexes, a new formulation was developed using PEI conjugated Pluronic F127 copolymer as an effective additive. Low molecular weight, branched polyethylenimine Mw 600 (LMW BPEI 600) was conjugated to the terminal end of Pluronic F127. The PEI-modified Pluronic copolymers formed a micellar structure in aqueous solution, similar to that of unmodified Pluronic copolymer. PEI modification of Pluronic copolymer increased the size of micelles while concomitantly raising the critical micelle concentration (CMC). The PEI-modified Pluronic copolymer was used as a micellar additive to enhance the gene transfection efficiency of pre-formulated polyelectrolyte complex nanoparticles composed of luciferase plasmid DNA and branched PEI Mw 25k (BPEI 25k) or polylysine Mw 39k (PLL 39k). The luciferase gene expression levels were significantly enhanced by the addition of the BPEI-modified Pluronic copolymer for the two formulations of BPEl and PLL polyplexes. The results indicated that the BPEI-modified Pluronic copolymer micelles ionically interacted on the surface of DNA/BPEI (PLL) polyplexes which might facilitate cellular uptake process.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.271-272
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• 2011

본 논문은 SOGI를 이용한 정상분 전압 검출을 기반으로 하는 SRF(synchronous reference frame)-PLL(phase locked loop) 시스템을 제안한다. 일반화된 2차 적분기의 이중으로 사용하여 QSG(Quadrature-signals generator)의 성능을 개선하여 전압 불평형, 고조파 왜곡 등으로 인한 오차 발생 시에도 빠르고 정확한 위상 검출이 가능하도록 하였으며 본 논문에서 제시한 알고리즘은 PSIM 프로그램 결과를 통하여 타당성을 입증한다.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.985-987
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• 2004

Switched Reluctance Motor(SRM) drive system is known to provide good torque characteristics and high efficiency drive. However, speed variation caused by higher torque ripple is one of main drawback. The Phase-Locked Loop (PLL) technique in conjunction with dynamic dwell angle control has good speed regulation characteristics. In this paper, appropriate advance angle control for high efficiency drive and PLL technique for accurate speed control is proposed. A TMS320F240 DSP is used to realize this drive system. Test results show that the system has good dynamic and precise speed control ability as well as high efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.967-971
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• 2004

The switched reluctance drive is known to provide good adjustable speed characteristics with high efficiency. However, higher torque ripple and lack of the precise speed control are drawbacks. In the paper, a PLL(Phase Locked Loop) technique is adopted to regulate the dwell angle instantaneously. A PLL control technique in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. The F240 DSP based control system is used to realize this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.

• Proceedings of the Optical Society of Korea Conference
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• 2009.10a
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• pp.241-242
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• 2009

Characterics of carrier-envelope-offset frequency ($f_{ceo}$) of a femtosecond laser stabilized by the direct locking method were investigated using two f-to-2f interferometers. The stability of $f_{ceo}$ was comaparable to that achieved with a conventional PLL method.