• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1289-1301
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• 1997

In a SDH network, one of the most important issues is the realization of network synchronization. In this paper, we presented the relationship between parameters and control algorithm of DP-PLL for design in a SDH based time, SSM processing time, PJE counter and reference switching time, and analyzed phase transients for one node and mutiple nodes through our simulation results with a standard specification. We suggested suitable design method of SDH-DP-PLL.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.87-88
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• 2014

The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1904-1917
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• 2016

The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAF-based PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.103-105
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• 2008

In grid-interconnection system, a fast, robust and precise phase angle detector is most important to grid synchronization and the active power control. The phase angle can be easily estimated by synchronous dq PLL system. On the other hand under unbalanced voltage condition, synchronous dq PLL system has problem that harmonics occur to phase angle or magnitude of grid voltage because of the effect of the negative sequence components. So, To eliminate the negative sequence components, the PLL method using APF (All Pass Filter) in a stationery reference frame to extract positive sequence components under unbalanced voltage condition is researched. In this paper, we propose a new PLL method with decoupling network using APF in a synchronous reference frame to extract the positive sequence components of the grid voltage under unbalanced grid. The cut-off frequency of APF in a synchronous reference frame can be set to twice of the fundamental frequency comparing with that of APF in a stationery reference frame which is the fundamental frequency. The proposed PLL strategy can detect the phase angle quickly and accurately under unbalanced gird voltages. Simulation and experimental results are presented to verify the proposed strategy under different kind of voltage dips.

• Journal of Power Electronics
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• v.15 no.1
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• pp.216-226
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• 2015

Grid synchronization is one of the key techniques for the grid-connected power converters used in distributed power generation systems. In order to achieve fast and accurate grid synchronization, a new phase locked loop (PLL) is proposed on the basis of the complex filter matrixes (CFM) orthogonal signal generator (OSG) crossing-decoupling method. By combining first-order complex filters with relation matrixes of positive and negative sequence voltage components, the OSG is designed to extract specific frequency orthogonal signals. Then, the OSG mathematical model is built in the frequency-domain and time-domain to analyze the spectral characteristics. Moreover, a crossing-decoupling method is suggested to decouple the fundamental voltage. From the eigenvalue analysis point of view, the stability and dynamic performance of the new PLL method is evaluated. Meanwhile, the digital implementation method is also provided. Finally, the effectiveness of the proposed method is verified by experiments under unbalanced and distorted grid voltage conditions.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.377-381
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• 2015

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.214-216
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• 2003

아날로그 NTSC 비디오 디코더 신호를 디코딩하여 디지털화된 컬러 값을 얻기 위해서는 컬러 버스트 신호를 동기화 해야 한다. 이 버스트 신호를 이용하여 Y. I. O의 값을 분리하기 때문이다. 아날로그 디코더의 경우에는 내부에 버스트 신호와 동기화 한 클럭을 PLL이나 DLL등을 이용하여 발생시켜서 I의 위치를 알아낸다. 비디오 신호 해독을 위한 전용의 PLL을 위해 아날로그 방식의 VLSI설계를 하는 것은 많은 노력이 들어갈 뿐만 아니라 특정 Fab에 종속되어 전체 칩의 이식성을 떨어뜨리게 된다. 본 논문에서는 아날로그 PLL이 없이도 디지털 입력데이터의 산술 연산을 통해서 컬러 버스트 동기화를 검출하는 방법을 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1543-1548
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• 2009

In this paper, a high speed code synchronization circuit is proposed. for fast code synchronization, matched filler method is used for initial code acquisition with two channel correlators. Particular frequency patterns of the limited number having the information about PN code start time are composed and transmitted repeatedly to increase the probability of accurate initial synchronization. And digital frequency synthesizer is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer.

• Journal of Power Electronics
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• v.14 no.5
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• pp.1057-1068
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• 2014

Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-used for grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of a SRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.9
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• pp.562-568
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• 2004

The frequency and phase angle of the utility voltage are important in many industrial systems. In the three-phase system, they can be easily known by using the utility voltage vector. However, in the case of single phase system, there are some difficulties in detecting the information of utility voltage. In conventional system, the zero-crossing detection method is widely used, but could not obtain the information of utility voltage instantaneously. In this paper, the new digital PLL control using virtual two phase detector is proposed with a detailed analysis of single-phase digital PLL control for utility connected systems. The experimental results under various utility conditions are presented and demonstrate an excellent phase tracking capability in the single-phase grid-connected operation.