• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2005년도 춘계학술대회논문집
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• pp.449-454
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• 2005

Brushless DC Motor(PM BLDCM) is widely used in industrial applications due to its high efficiency and power density. In order to increase reliability and reduce system cost, this paper studies particularly applicable method for sensorless PM BLDCM drive system. The resulting third harmonic signal keeps a constant phase relationship with the rotor flux for any motor speed and load condition, and is practically free of noise that can be introduced by the inverter switching, making this a robust sensing method. As a result, the method described here is not sensitive to filtering delays, allowing the motor to achieve a good performance over a wide speed range. In addition, a simple starting method and a speed estimation approach are also proposed.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.87-88
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• 2011

본 논문은 최근 빠른 속도로 성장하고 있는 신재생에너지 분야 중 태양광을 이용한 계통연계형 PV PCS의 PLL(Phase Locked Loop) 기법을 DSP로 처리할 수 있도록 디지털 논리회로로 구현하는 DPLL(Digital Phase Locked Loop) 기법을 제시하고 모델링과 시뮬레이션을 통하여 검증한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.684_685
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• 2009

A digital sampling algorithm that uses a two high resolution integrating Voltmeters which are synchronized by Phase Lock Loop (PLL) time clock for accurately measuring the parameters, active and reactive power, for sinusoidal power measurements is presented. The PLL technique provides high precision measurements, root mean square (rms), phase and complex voltage ratio, of the AC signal. The system has been designed to be used at the Korean Research Institute of Standards and Science (KRISS) as a reference power standard for electrical power calibrations. The test results have shown that the accuracy of the measurements is better than $10 {\mu}W/VA$ and the level of uncertainty is valid for the power factor range zero to 1 for both lead and lag conditions. The system is fully automated and allows power measurements and calibration of high precision wattmeters and power calibrators at the main power frequencies 50 and 60 Hz.

• Journal of Yeungnam Medical Science
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• 제6권2호
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• pp.63-70
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• 1989

This paper describes to design and to examine the mechanical characteristics of high frequency jet ventilator. The device consists of Phase lock loop(PLL) system, solenoid valve driving control part and Air regulating system. This study is carried out by changing several factors such as endotracheal tube(E.T. tube)diameter, injector cannula diameter, 1%, and frequency(breaths/mim.) having direct effects on the gas exchange as well as parameters of the entrained gas by venturi effects, so as to measure the tidal volume and minute volume. This system characteristics were as follows : 1) Frequency : 6-594bpm 2) Inspiration time : 1-99% 3) Variance of input air pressure : 1-30PSI.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 추계종합학술대회
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• pp.176-179
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• 2000

통신회로에서 많이 사용되는 PLL 방식에 의한 주파수 합성기는 여러 장점이 있지만 위상잡음 특성이 나쁘고 긴 주파수 도약 시간을 갖기 때문에, 최근의 고속(1$\mu\textrm{s}$이하)으로 주파수 호핑(Frequency Hopping)을 요구하는 디지털 통신 시스템에서는 사용이 어렵다. 본 연구는 디지털 영상 패턴 발생기에서 1600hops/s로 600개 이상의 랜덤한 주파수를 발생하는 주파수합성기를 DDS (Direct Digital Synthesis) 방식을 이용하고, CPLD에 의해 구현하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.967-971
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• 2004

The switched reluctance drive is known to provide good adjustable speed characteristics with high efficiency. However, higher torque ripple and lack of the precise speed control are drawbacks. In the paper, a PLL(Phase Locked Loop) technique is adopted to regulate the dwell angle instantaneously. A PLL control technique in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. The F240 DSP based control system is used to realize this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.

• Journal of Communications and Networks
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• 제8권1호
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.482-484
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• 2006

This paper describes fast-hopping frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432MHz, 3960MHz, 4488MHz) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224MHz. The second uses three PLLs operating at corresponding center frequencies. The third employes two PLLs operating at 3960MHz and 528MHz. Simulation results using a 0.18um RF CMOS process parameters show that the third structure exhibit the best characteristics. The band switching time of the proposed synthesizer is less than 1.3ns and the spur is less than -36dBc. The synthesizer consumes 22mA from a 1.8V supply.

• 대한약학회:학술대회논문집
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• 대한약학회 2002년도 Proceedings of the Convention of the Pharmaceutical Society of Korea Vol.2
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• pp.246.2-247
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• 2002

In this study. we tried to investigate whether polymerized basic amino acid e.g. poly-L-lysine(PLL) which has the molecular weight under 10 kD significantly affects the physiological and stimulated mucin release from cultured hamster tracheal surface epithelial cells. Confluent primary hamster tracheal surface epithelial(HTSE) cells were metabolically radiolabeled with 3H-glucosamine for 24 hr and chased for 30 min in the presence of either PLLs or adenosine triphosphate(ATP) and PLL to assess the effects on basic or ATP-stimulated 3H-mucin release. (omitted)

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.