• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.320-324
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• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.270-279
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• 2018

This paper elucidates a hysteresis current controller for enhancing the performance of static synchronous compensator (STATCOM) using cascaded H-bridge multilevel inverter. Due to the rising power demand and growing conventional generation costs a new alternative in renewable energy source is gaining popularity and recognition. A five level single phase cascaded multilevel inverter with two separated dc sources, which is energized by photovoltaic - wind hybrid energy source. The voltages across the each dc source is balanced and standardized by the proposed hysteresis current controller. The performance of STATCOM is analyzed by connecting with grid connected system, under the steady state & dynamic state. To reduce the Total Harmonic Distortion (THD) and to improve the output voltage, closed loop hysteresis current control is achieved using PLL and PI controller. The performance of the proposed system is scrutinized through various simulation results using matlab/simulink and hardware results are also verified with simulation results.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.435-438
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• 2006

위성신호는 저앙각에 위치하거나 재밍 및 간섭신호의 영향을 받으면 약해진다. 이러한 약신호를 안정적으로 추적하기 위해서는 신호추적루프의 대역폭이 가능하면 작아야 한다. 그러나 작은 대역폭의 신호추적루프는 고기동 환경에서 기준주파수의 주파수오차를 포함한 입력오차가 커져 불안정해진다. 본 논문에서는 최대 저크 15g/s의 동적특성을 가지는 항체의 항법정보를 획득하고 동시에 28dB-Hz의 약신호도 안정적으로 추적할 수 있는 신호추적루프를 연구한다. 이를 위해 위성신호 상태를 예측할 수 있는 SNR, 앙각, 항체의 가속도 등을 고려하여 대역폭 및 PIT를 가변적으로 설계한 적응형 신호추적루프를 설계한다. 또한 약신호인 C/No 28dB-Hz 신호를 안정적으로 추적하기 위해 10ms의 PIT(Predetection Integration Time)와 비트동기를 고려한 Coherent 방식을 적용한 반송파 위상추적루프를 설계한다. 이렇게 설계된 신호추적루프의 성능을 검증하기 위해 항체의 동적환경과 위성신호 크기를 묘사해줄 수 있는 시뮬레이터를 이용하여 위성신호 추적성능을 시험하고 결과를 분석한다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.2
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• pp.93-99
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• 1989

This paper describes Sinusoidal Wave-Variable Voltage Variable Fequency (SW-VVVF) system for the high efficiency drive of a 3-phase induction motor. SW-VVVF system consists of a 3-phase 24-pulse converter and a SPWM inverter. The converter with additional 2 tap diode circuits in interphase reactor reduces harmonics in input current. The SPWM inverter consists of an improved PLL system and a V/F controller, which reduces harmonics in output current and performs a high efficiency algorithm by maintaining a constant slip frequency and compensating for the velocity variation of the induction motor with the change of load. Therefore, this system reduces harmonics in input and output currents, and also can drive an induction motor with high efficiency in an economical way. We have proved its utility through experiment.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.8
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• pp.417-425
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• 1999

This paper presents an effective control scheme with the voltage-fed half-bridge series resonant inverter for induction heating system, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuits. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching) irrespective of sensitive load parameter variations, specially in the non-magnetic materials as well as power regulation. The detail operation principle and the characteristics of inverter system with the proposed control scheme are described and its validity is verified by the simulation and the experimental results for a prototype induction cooking system rated at 1.2kW.

• Journal of Power Electronics
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• v.16 no.1
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• pp.310-318
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• 2016

This paper presents a new orthogonal signals generator (OSG) with DC Offset rejection for implementing a phase locked loop (PLL) in single-phase grid-connected power systems. An adaptive filter (AF) based on the least mean square (LMS) algorithm is used to constitute the OSG in this study. The DC offset in the measured grid voltage signal can be significantly rejected in the developed OSG technique. This generates two pure orthogonal signals that are free from the DC offset. As a result, the DC offset rejection performance of the presented single-phase phase locked loop (SPLL) can be enhanced. A mathematical model of the developed OSG and the principle of the adaptive filter based SPLL (AF-SPLL) are presented in detail. Finally, simulation and experimental results demonstrate the feasibility of the proposed AF-SPLL.

• Journal of Power Electronics
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• v.12 no.6
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• pp.851-858
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• 2012

This paper presents resonant inverter tuning for current source parallel resonant induction heating systems based on a new self oscillating switching technique. The phase error is suppressed in a wide range of operating frequencies in comparison with Phase Locked Loop (PLL) techniques. The proposed switching method has the capability of tuning under fast changes in the resonant frequency. According to this switching method, a multi-frequency induction heating (IH) system is proposed by using a single inverter. In comparison with multi-level inverter based IH systems, the advantages of this technique are its simple structure, better transients and wide range of operating frequencies. A laboratory prototype was built with an operating frequency of 35 kHz to 55 kHz and 300 W of output power. The performance of the IH system shows the validity of the new switching technique.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.428-430
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• 2007

Converter that is dc source equipment source's phase by reference control function that detect source's phase because should be done compulsorily use. Source's phase detect method there be method that use source's ac voltage directly by signal, and use methods that voltage detects status by PLL method and so on via point that '0' becomes usually. All above methods to detect phase are using, wrong action of phase detector converter's ailment or converter of burn can. Ths paper compares and examined usable phase detection method in source's frequency fluctuation presuming source's frequency using observer.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.441-443
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• 2007

In this paper, The authors design the current controller which independently control the d, q axis current transformed by the synchronously rotating d, q axis and a Space Vector Pulse Width Modulation(SVPWM) to steadily control the output DC-Link voltage against the variable load of the three phase PWM converter. Also, This study improves the high power factor, stability, and rapid response by the phase angle control using the digital Phase Locked Loop(PLL).

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1301-1303
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• 1996

A new automatic frequency control(AFC) tracking algorithm, which we call a rotational decision directed AFC(RDDAFC) is proposed for QPSK demodulation at the digital direct broadcasting satellite(DBS). In order to prevent the presence of the residual phase difference between symbols received at k and k-l by the CPAFC[1] as well as the AFC based on $tan^{-1}$ circuit[2], the RDDAFC rotates the decision boundary for the kth received symbol by the frequency detector output of the (k-1)th received symbol before passing through the cross product discriminator. Test results show that the total pull-in time of the RDDAFC and PLL was 0.13msec under a carrier frequency offset of 2.4MHz when S/N equals 2dB.