• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1471-1475
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• 1987

This paper proposes testable design of sequential NMOS PLAs. The extra bit lines and devices are added to the conventional PLAs. The time is taken to assigning devices in the extra bit lines, which is excessive in the conventional method, is reduced by using the symmetrical distance matrix of the PLA and the regular assigning method. As a result, the test patterns can be easily generated. Also, the silicon area overhead of extra hardware is low.

• 한국군사과학기술학회지
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• 제8권1호
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• pp.25-31
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• 2005

PLA(Passive Linear Array) system has been primarily utilized to detect and track underwater targets, such as submarines. This system has difficulty in distinguishing between underwater targets and surface ships in a dense target environment. And a single-PLA system does not provide target state observability. At least two PLAs are necessary to observe a track uniquely. To classify and localize the underwater targets effectively, first of all, it is very of importance to discriminate the surface ships in the multi-target environment. These problems can be overcome by the association of distributed PLAs and radars. In this paper, we present an algorithm to solve the track-to-track association of the heterogeneous data from three PLAs and one radar are noncollocated with known sensor positions. Also, this paper shows the simulation results to verify the proposed algorithm.

• Journal of Ginseng Research
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• 제48권4호
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• pp.428-434
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• 2024

Background: Platelet-leukocyte aggregates (PLAs) play important roles in cardiovascular disease and sepsis. Red ginseng extract (RGE) has been well-studied for its antiplatelet and anti-inflammatory activities. However, the potential inhibitory effects of RGE on PLA have not been investigated. Methods: Six-week-old ICR mice were given oral gavage of RGE for 7 days, followed by an intraperitoneal injection of 15 mg/kg of lipopolysaccharide. Mice were euthanized 24 h later, and blood samples were collected for further analysis. Flow cytometry was utilized to sort populations of PLAs and platelet-neutrophil aggregates (PNAs). By using confocal microscopy, PNAs were validated. Morphological changes in platelets and leukocytes were visualized with scanning electron microscopy. Expressions of tissue factor (TF) and platelet factor 4 (PF4) were investigated using enzyme-linked immunosorbent assay. Results: Populations of activated platelets, PLAs and PNAs, were significantly increased with LPS-induction. Treatment with 200 and 400 mg/kg of RGE decreased platelet activation. Moreover, the populations of PLAs and PNAs were reduced. PNAs were visible in the blood of septic mice, and this was attenuated by treatment with 400 mg/kg of RGE. Morphologically, sepsisinduced platelet activation and fibrin formation in the blood. This was reduced with RGE treatment. Sepsis-induced increase in the plasma levels of TF and PF4 was also reduced with RGE treatment. Conclusion: This study shows that RGE is a potential therapeutic that reduces the activation of platelets and targets PLA and PNA formation. Detailed inhibitory mechanisms of RGE should be studied.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.233-234
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• 2006

In this paper, Via hole pore were investigated during PLAS (PessureLess Assisted Constrained Sintering) process of LTCC. Ag and Ag-Pd paste mixture were tested for via paste. Ag paste with 10~25% Ag-Pd paste showed no via hole pore, but further increase of Ag-Pd contents in via paste increased via pore. From shrinkage curve, 10~25% Ag-Pd paste showed expansion behaviors before shrink and this phenomena result in the reduction of via hole pore during PLAS process.

• 폴리머
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• 제36권3호
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• pp.309-314
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• 2012

생분해성 폴리락타이드의 분해속도를 조절하기 위하여 $d$-lactide와 $l$-lactide의 함량을 달리하여 다양한 stereochemical PLAs를 개환중합으로 합성하고 Langmuir 단분자막 장치를 이용하여 알칼리 분해속도를 측정하였다. 알칼리 수용액상에서 혼합 단분자막의 분해속도를 각 혼합고분자의 광학적 순도(100, 99, 97, 95%)의 항으로 측정하였다. 스테레오 콤플렉스에 기인하는 혼합물의 용융온도는 혼합물 성분의 광학적 순도가 증가함에 따라 증가하였다. 분해거동은 100% 광학적 순도를 가진 혼합물은 각 단일중합체보다 느린 분해속도를 나타내는 반면 다른 혼합물들은 2단계의 분해거동을 나타내었는데 1단계에서는 콤플렉스를 형성하지 않은 부분에서의 분해로 단일중합체에 비해 빠른 분해속도를 나타내었고 2단계에서는 100% 광학적 순도를 가진 혼합물과 유사하게 느린 분해속도를 나타내었다. 이러한 결과는 폴리락타이드의 stereochemistry와 스테레오 콤플렉스를 이용하여 알칼리 분해속도를 조절할 수 있음을 의미한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.194-195
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• 2006

개인 휴대 통신 기기의 급속한 발달로 인해 부품의 소형화, 고집적화가 중요한 요소로 대두되고 있으며 이를 위해서는 모듈내부에 3차원적인 수동소자의 내장이 가능한 LTCC (Low Temperature Co-fired Ceramics) 공정이 각광받고 있다. Embedded Capacitor를 제조하기 위해 유전율이 7.6과 6.5인 LTCC 재료를 이종접합 하여 제조하였으며 이종재료의 수축거동 차이에 의한 camber가 발생하였다. 이를 해결하고 또한 고주파 부품용 정밀회로 패턴을 구 현하기 위해 PLAS 방식의 Constrained Sintering 공정을 적용하여 camber 문제를 해결하였으며 capacitance 값이 두 이종재료의 유전율과 1:1로 비례하지 않았는데 이는 유전율 65 tape에 잔존하는 기공 때문으로 판단되며 미세구조로써 확인하였다.

• 한국전기전자재료학회논문지
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• 제26권12호
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• pp.924-927
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• 2013

In this study, we proposed CMP-PLAs to replace the Al heat sinks as heat sink materials, and investigated heat dissipation characteristics of the LED lighting devices using them. The crystallinity of the proposed CMP-PLA heat sinks decreased with increasing carbon nanotube contents in CMP-PLA. However, the thermal conductivity was improved with the increase of the carbon nanotube contents. The heat dissipation characteristics of the LED lighting devices using CMP-PLA heat sinks was improved with increasing carbon nanotube contents in CMP-PLA. For the LED lighting devices using CMP-PLA heat sinks with 40% carbon nanotube contents, the initial temperature measured at the heat sink plate was $27^{\circ}C$, which increased as time, and it was saturated around $56^{\circ}C$ after an hour. The LED lighting devices using CMP-PLA heat sinks are expected to be functional materials that can reduce their weight and improve their electric properties, compared to those using existing Al heat sinks.

• 펄프종이기술
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• 제41권4호
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• pp.8-14
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• 2009

Characteristics of biodegradable polymers for mulching mat for seedling were investigated. The solvent solubility of polymers is highest in methylene chloride and chloroform. Tensile strength and breaking elongation of polymer dipped paper were increased to the 0.43-1.46 kN/m and the 0.03-0.26%, respectively. PLAs had showed lower glass transition temperature and melting point than those of polyester. As a result, PLA should be most suitable polymer for mulching mat manufacturing. After biodegradation of polymers by lipase, surface of polymers was change to more flat due to enzymatic degradation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1507-1511
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• 1987

This paper proposes a NAND-NAND logic sequential Programmable Logic Array (PLA) using CMOS technology, and test generation methods about stuck-open faults. By using LSSD (Level Sensitive Scan Design) method instead of Flip-Flops in Sequential PLA, the complex test problems of sequential logic are simplified. After generating the test sets using connection graph, regular test sequences and all transistor faults detection method in PLA are proposed. Finally, by programming these algorithms in PASCAL at VAX 8700 and adopting these to pratical CMOS Sequential PLA circuits, we proved the effectiveness of this design.

• 대한전자공학회논문지
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• 제26권10호
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.