• 제목/요약/키워드: PCI Express Bus

검색결과 13건 처리시간 0.017초

채널기반형 네트웍에서의 IPoIB 프로토콜 성능평가 (A Performance Evaluation for IPoIB Protocol in Channel based Network)

  • 전기만;민수영;김영환
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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    • pp.687-689
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    • 2004
  • As using of network increases rapidly, performance of system has been deteriorating because of the overhead and bottleneck. Nowadays, High speed I/O network standard, that is a sort of PCI Express, HyperTransport, InfiniBand, and so on, has come out to improve the limites of traditional I/O bus. The InfiniBand Architecture(IBA) provides some protocols to service the applications such as SDP, SRP and IPoIB. In our paper, We explain the architecture of IPoIB (IP over InfiniBand) and its features in channel based I/O network. And so we provide a performance evaluation result of IPoIB which is compared with current network protocol. Our experimental results also show that IPoIB is batter than TCP/IP protocol. For this test, We use the dual processor server systems and Linux Redhat 9.0 operating system.

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고속 채널 기반 네트웍에서 SDP 프로토콜 성능 평가 (A Performance Evaluation for SDP(Socket Direct Protocol) in Channel based Network)

  • 박창원;김영환
    • 정보통신설비학회논문지
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    • 제3권2호
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    • pp.18-25
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    • 2004
  • As using of network Increases rapidly, performance of system has been deteriorating because of the overhead and bottleneck. Nowadays, high speed I/O network standard, that is a sort of InfiniBand, PCI Express and so on, has come out to improve the limites of traditional I/O bus. The InfiniBand provides some protocols to service the applications such as SDP, SRP and IPoIB. In our paper, We explain the architecture of SDP(Socket Direct Protocol) and its features in channel based I/O network. And so, we provide a result of performance evaluation of SDP which is compared with current network protocol. Our experimental results also show that SDP is better than TCP/IP protocol.

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Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

  • Tan, Fern-Nee;Lee, Sheng Chyan
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.69-74
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    • 2013
  • In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.