• 한국시뮬레이션학회논문지
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• 제15권4호
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• pp.59-67
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• 2006

본 연구에서는 갠트리타입 기종을 사용한 PCB 조립 생산시 생산시스템의 수행도 향상을 위한 방안을 개발하여 제시한다. 갠트리타입의 기종에서는 헤더나 슬롯의 이동보다는 노즐의 교체가 시스템의 수행도 향상에 주된 걸림돌이 되므로 동시흡착을 최대화할 수 있는 방안을 모색하였다. 본 연구에서 제시된 해법은 피더의 위치와 노즐의 위치를 감안하여 동시흡착을 수행하도록 함으로써 노즐 교체를 최소화하고, 기판당 조립시간의 감소도 이루어지도록 하였다. 제안 해법의 유효성을 입증하기 위해 시뮬레이션 모형을 구축하고 부품의 수를 변화시켜가면서 다음 작업대상피더와 교체노즐의 선정을 다양하게 하여 여러 운영방안들의 수행도와 비교 분석하였다. 시뮬레이션 결과, 동시흡착을 유도하는 노즐교체를 할 경우 전반적인 수행상태가 양호한 것으로 나타났다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.1237-1240
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• 1996

This paper proposes a heuristic algorithm for performing the line balancing of PCB assembly fine including multiple surface mounters efficiently. We consider a PCB assembly line including the multiple surface mounters arranged serially as a target system. We assume that the number of heads of surface mounters can be changed. Also, the conveyor is assumed to move at a constant speed and have no buffer. Considering the minimum number of machines required for the desired production rate is a discrete nonincreasing function which is inversely proportional to the cycle time, we propose an optimization algorithm for line balancing by using the binary search method. Also we propose an head-changing algorithm. The algorithms are validated through the computer simulation.

• 한국컴퓨터정보학회논문지
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• 제21권3호
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• pp.57-64
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• 2016

This paper deals with the PCB assembly time minimization problem that the PAP (pick-and-placement) machine pickup the K-weighted group of N-components, loading, and place into the PCB placement location. This problem considers the rotational turret velocity according to component weight group and moving velocity of distance in two component placement locations in PCB. This paper suggest heavy-weight component group first pick-and-place strategy that the feeder sequence fit to the placement location Hamiltonean cycle sequence. This algorithm applies the quadratic assignment problem (QAP) that considers feeder sequence and location sequence, and the linear assignment problem (LAP) that considers only feeder sequence. The proposed algorithm shorten the assembly time than iATMA for QAP, and same result as iATMA that shorten the assembly time than ATMA.

• 산업공학
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• 제18권3호
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• pp.297-307
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• 2005

PCB assembly is a complicated and difficult process to optimize due to the necessity of simultaneous consideration of component’s rack assignment and board mounting sequencing. An efficient PCB assembly method is developed by using neighboring positioned identical components information as well as quantity and size of the components. It is found that same type of components are located closely each other by checking real PCBs and interviewing with PCB designers in practice. Better performance of the developed procedure is obtained along with more number of total components and more number of neighboring positioned identical components cases. Simulation models are developed using Visual C++ for performance evaluation purposes of the suggested heuristic.

• 제어로봇시스템학회논문지
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• 제3권4호
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• pp.381-388
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• 1997

This paper proposes a heuristic algorithm to efficiently perform line balancing in the PCB assembly line including multiple surface mounters efficiently. Generally, the problems in line balancing are classified into two kinds. Firstly, is the determining of the minimum number of machines required for achieving the desired production rate. Secondly, is the assign of jobs to multiple machines in order to minimize the cycle time which is defined as a maximum among the working times of machines when the number of machines is fixed. In this paper, we deal with the latter. We consider a PCB assembly line, including the multiple surface mounters arranged serially as a target system. Also, the conveyor is assumed to move at a constant speed and have no buffer. Considering that the minimum number of machines required for the desired production rate is a discrete nonincreasing function which is inversely proportional to the cycle time, we propose an optimization algorithm for line balancing by using the binary search method. The algorithm is validated through computer simulation, the results of which show that their shapes coincide nearly with those of optimal line balancing efficiency graphs regardless of the number of components, the performance of surface mounters, and the structure of assembly line.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• 제어로봇시스템학회논문지
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• 제11권2호
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• pp.144-151
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• 2005

We propose an optimization method to reduce the assembly time of chip mounters. Feeder arrangement and assembly sequence are determined considering the multiple feeder assignment. The problem is divided into two sub-problems: feeder arrangement problem and assembly sequence problem. We present mathematical model for each sub-problem. The clustering algorithm and assignment algorithm are applied to solve the feeder arrangement problem. The assignment algorithm and connection algorithm are applied to solve the assembly sequence problem. Simulation results are then presented to verity the usefulness of the proposed method.

• International Journal of Control, Automation, and Systems
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• 제4권1호
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• pp.96-104
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• 2006

We propose a path planning method to improve the productivity of AOI (automated optical inspection) machines in PCB (printed circuit board) assembly lines. The path-planning problem is the optimization problem of finding inspection clusters and the visiting sequence of cameras to minimize the overall working time. A unified method is newly proposed to determine the inspection clusters and visiting sequence simultaneously. We apply a hybrid genetic algorithm to solve the highly complicated optimization problem. Comparative simulation results are presented to verify the usefulness of the proposed method.

• 전기학회논문지
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• 제61권3호
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• pp.472-478
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• 2012

The inspection machine in PCB (printed circuit board) assembly line checks assembly errors by inspecting the images inside of the component inspection region. The component inspection region consists of region of component package and region of soldering. It is necessary to extract the regions automatically for auto-teaching system of the inspection machine. We propose an image segmentation method to extract the component inspection regions automatically from images of PCB. The acquired image is transformed to HSI color model, and then segmented by several regions by clustering method. We develop a modified K-means algorithm to increase the accuracy of extraction. The heuristics generating the initial clusters and merging the final clusters are newly proposed. The vertical and horizontal projection is also developed to distinguish the region of component package and region of soldering. The experimental results are presented to verify the usefulness of the proposed method.

• 한국시뮬레이션학회논문지
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• 제14권2호
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• pp.25-34
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• 2005

Determination of component mounting sequence on printed circuit board assembly process is a typical NP-hard problem. It is a kind of traveling salesman problems, but it has one more hard to meet constraint of matching component type per mounting position as well as searching the shortest path. An efficient method is developed by separation of crowed area and allowing up to two slots per component type. A simulation model is constructed using Visual C++ for evaluation of the suggested heuristic.