• Journal of electromagnetic engineering and science
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• v.7 no.1
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• pp.7-11
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• 2007

PCB Power-Bus (comprising power/ground planes) impedance and fields are evaluated by an efficient series expansion method that is suggested in this paper. It is used to investigate the structure's radiated emission(RE) levels and find acceptable ways of loading the power/ground planes such as decoupling capcitor(DeCap)s, balanced feeding and slits, in order to reduce the interferences. Also, the calculations and measurements of a proposed geometry are verified by vector fitting as a analysis model to check the behavior of the slit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.7
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• pp.1065-1073
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• 1999

This paper analyzed the ground bounce caused by the power plane resonance in the multilayered printed circuit board(PCB) using the Haar-wavelet-based Multiresolution Time-Domain (MRTD). In conventional Finite-Difference Time-Domain(FDTD), the highly fine vertical cell is needed to represent the distance between $V_{cc}$ plane and ground plane since the two planes are very close. Therefore the time step $\Deltat$ must be very small to satisfy the stability condition. As a result, a large number of iterations are needed to obtain the response in wanted time. For this problem, this paper showed that the computation time can be reduced by application of the MRTD method. The results obtained by the MRTD agree very well with those by FDTD method and analytic solutions. In conclusion, this paper proved the efficiency and accuracy of MRTD method for analyzing the EMI/EMC problems in PCB.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.68-74
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• 2002

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

• Journal of IKEEE
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• v.25 no.4
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• pp.591-597
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• 2021

This paper proposes an EMC-aware PCB design method to reduce electromagnetic emission, where trace length and teturn path of critical signal are shortened by changing chip location and trace layout on the PCB, while additional filters or decoupling capacitors are not required. In the proposed method, signal velocity is calculated for various signals on the PCB. Critical signal with the fastest signal velocity is determined and its return path is shortened as much as possible by placing chip location and trace routing first. Return path of critical signal should be carefully designed not to have discontinuity. Power plane and ground plane should be carefully designed not to be divided, since these planes are the reference of return path. The proposed method was applied to automotive directional Bluetooth speaker which failed to pass CISPR 32 and CISPR 25 EMC tests. Its PCB was redesigned based on the proposed method and it easily passed the EMC tests. The proposed method is useful to EMC-sensitive electronic equipments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.633-643
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• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.