• Title/Summary/Keyword: PCB 검사

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A Study on the Test Strategy Based on SSA Technique for the Digital Circuit Boards in Production Line (SSA 기법에 기반한 생산조립라인의 디지털 부품 실장 PCB의 검사전략에 대한 연구)

  • Jung Yong-Chae;Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.4
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    • pp.243-250
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    • 2005
  • Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

Design of a Rule-Based Solution Based on MFC for Inspection of the Hybrid Electronic Circuit Board (MFC 기반 하이브리드 전자보오드 검사를 위한 규칙기반 솔루션 설계)

  • Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.9
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    • pp.531-538
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    • 2005
  • This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

Implementation of Large Area CMOS Image Sensor Module using the Precision Align Inspection (정밀 정렬 검사를 이용한 대면적 CMOS 이미지 센서 모듈 구현)

  • Kim, Byoungwook;Kim, Youngju;Ryu, Cheolwoo;Kim, Jinsoo;Lee, Kyungyong;Kim, Myungsoo;Cho, Gyuseong
    • Journal of Radiation Industry
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    • v.8 no.3
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    • pp.147-153
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    • 2014
  • This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a $2{\times}1$ butted CMOS image sensor module which except for the size of PCB is $170mm{\times}170mm$. And the pixel size is $55{\mu}m{\times}55{\mu}m$ and the number of pixels is $3,072{\times}3,072$. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

A Study on the Test Strategy of Digital Circuit Board in the Production Line Based on Parallel Signature Analysis Technique (PSA 기법에 근거한 생산라인상의 디지털 회로 보오드 검사전략에 대한 연구)

  • Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.11
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    • pp.768-775
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    • 2004
  • The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

Feasibility of Single-Shot Dual-Energy X-ray Imaging Technique for Printed-Circuit Board Inspection (인쇄회로기판 검사를 위한 단일조사 이중에너지 엑스선 영상기법의 유용성에 관한 연구)

  • Kim, Seung Ho;Kim, Dong Woon;Kim, Daecheon;Kim, Junwoo;Park, Ji Woong;Park, Eunpyeong;Kim, Jinwoo;Kim, Ho Kyung
    • Journal of Radiation Industry
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    • v.9 no.3
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    • pp.137-141
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    • 2015
  • A single-shot dual-energy x-ray imaging technique has been developed using a sandwich detector by stacking two detectors, in which the front and rear detectors respectively produce relatively lower and higher x-ray energy images. Each detector layer is composed of a phosphor screen coupled with a photodiode array. The front detector layer employs a thinner phosphor screen, whereas the rear detector layer employs a thicker phosphor screen considering the quantum efficiency for x-ray photons with higher energies. We have applied the proposed method into the inspection of printed circuit boards, and obtained dual-energy images with background clutter suppressed. In addition, the single-shot dual-energy method provides sharper-edge images than the conventional radiography because of the unsharp masking effect resulting from the use of different thickness phosphors between the two detector layers. It is promising to use the single-shot dual-energy x-ray imaging for high-resolution nondestructive testing. For the reliable use of the developed method, however, more quantitative analysis is further required in comparisons with the conventional method for various types of printed circuit boards.

Optimization of Soldering Process of Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.7Cu-1.6Bi-0.2In Alloys for Solar Combiner Junction Box Module (태양광 접속함 정션박스 모듈 적용을 위한 Sn-3.0Ag-0.5Cu 및 Sn-1.0Ag-0.7Cu-1.6Bi-0.2In 솔더링의 공정최적화)

  • Lee, Byung-Suk;Oh, Chul-Min;Kwak, Hyun;Kim, Tae-Woo;Yun, Heui-Bog;Yoon, Jeong-Won
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.3
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    • pp.13-19
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    • 2018
  • The soldering property of Pb-containing solder(Sn-Pb) and Pb-free solders(Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.7Cu-1.6Bi-0.2In) for solar combiner box module was compared. The solar combiner box module was composed of voltage and current detecting modules, diode modules, and other modules. In this study, solder paste printability, printing shape inspection, solder joint property, X-ray inspection, and shear force measurements were conducted. For optimization of Pb-free soldering process, step 1 and 2 were divided. In the step 1 process, the printability of Pb-containing and Pb-free solder alloys were estimated by using printing inspector. Then, the relationship between void percentages and shear force has been estimated. Overall, the property of Pb-containing solder was better than two Pb-free solders. In the step 2 process, the property of reflow soldering for the Pb-free solders was evaluated with different reflow peak temperatures. As the peak temperature of the reflow process gradually increased, the void percentage decreased by 2 to 4%, but the shear force did not significantly depend on the reflow peak temperature by a deviation of about 0.5 kgf. Among different surface finishes on PCB, ENIG surface finish was better than OSP and Pb-free solder surface finishes in terms of shear force. In the thermal shock reliability test of the solar combiner box module with a Pb-free solder and OSP surface finish, the change rate of electrical property of the module was almost unchanged within a 0.3% range and the module had a relatively good electrical property after 500 thermal shock cycles.

Comparison of Cleaning Performance of CFC 113 and the Alternatives (CFC 113과 대체세정제의 세정성능 비교)

  • Row, Kyung Ho;Choi, Dai-Ki;Lee, Youn Yong
    • Analytical Science and Technology
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    • v.6 no.5
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    • pp.521-530
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    • 1993
  • According to the Montreal Protocol, CFC 113, one of the ozone-depleting substances, will be prohibited to use as a cleaning solvent essentially in the electronic industry. Therefore, the development of the alternative cleaning solvents to CFC 113 is being accelerated. A number of the alternative cleaning solvents are avialable on the market. The alternatives of Axarel 32(DuPont), Cleanthru 750H(KAO Chemical), and EC-Ultra(Petroferm) are chosen for the comparison of cleaning performance with CFC 113. The test methods for measuring the cleaning performance were composed of the measurement of the physical properties, the experiments on the material compatibility with cleaning solvents, the measurement of the evaporation rate, and finally the experiments of the removal efficiency. Normally the basic physical properties of the alternatives had higher boiling points, viscosity and surface tension, which were quite different to those of CFC 113. In terms of solubility of rosin-based flux, the solubilities of abietic acid (nonpolar organic) were similar, but those of the activator (polar organic) in the alternatives were better than CFC 113. The evaporation of the alternatives was very slow, compared to CFC 113, which had much lower boiling point. All the cleaning solvents showed the good material compatibility with FR4 and Cu-coated PCB. The better removal efficiencies of abietic acid were obtained when using the ultrasonic mechanical energy over the dipping method. The experiments also indicated the very slow-eavaporating solvent was not desirable with the dipping cleaning method, and the differences in the removal efficiency of the alternatives with the ultrasonic cleaning method were negligible. Among the alternatives, the overall cleaning performances were obsorved as almost similar. Before selecting the ultimate cleaning solvent, the application of cleaning machine, environmental issues, and economics are simultaneously considered with the cleaning performance.

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The Risk Assessment of Carbon Monoxide Poisoning by Gas Boiler Exhaust System and Development of Fundamental Preventive Technology (가스보일러 CO중독 위험성 예측 및 근원적 예방기술 개발)

  • Park, Chan Il;Yoo, Kee-Youn
    • Journal of the Korean Institute of Gas
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    • v.25 no.3
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    • pp.27-38
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    • 2021
  • We devised the system to automatically shutdown the boiler and to fundamentally block the harmful gases, including carbon monoxide, into the indoor when the exhaust system swerves: (1) The discharge pressure of the exhaust gas decreases when the exhaust pipe is disconnected. The monitoring system of the exhaust pipe is implemented by measuring the output voltage of APS(Air Pressure Sensor) installed to control the amount of combustion air. (2) The operating software was modified so that when the system recognizes the fault condition of a flue pipe, the boiler control unit displays the fault status on the indoor regulator while shutting down the boiler. In accordance with the ventilation facility standards in the "Rules for Building Equipment Standards" by the Ministry of Land, Infrastructure and Transport, experiments were conducted to ventilate indoor air. When carbon monoxide leaked in worst-case scenario, it was possible to prevent poisoning accidents. However, since 2013, the number of indoor air exchange times has been mitigated from 0.7 to 0.5 times per hour. We observed the concentration exceeding TWA 30 ppm occasionally and thus recommend to reinforce this criterion. In conclusion, if the flue pipe fault detection and the indoor air ventilation system are introduced, carbon monoxide poisoning accidents are expected to decrease significantly. Also when the manufacturing and inspection steps, the correct installation and repair are supplemented with the user's attention in missing flue, it will be served to prevent human casualties from carbon monoxide poisoning.