• Title/Summary/Keyword: PC packer

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Grouting Injection Effectiveness of a Permeable Compacting Grout using Permeable Compaction Type Packer (침투다짐형 팩커를 이용한 침투다짐 그라우트의 주입 효과)

  • Park, Sung-Yong;Shim, Houng-Gen;Kang, Hee-Jin;Lim, One-Bin;Kim, Yong-Seong
    • Journal of the Korean Geosynthetics Society
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    • v.16 no.2
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    • pp.149-158
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    • 2017
  • Permeating injection is commonly known as an ideal type of injection in grouting reservoir embankment, yet often-combined permeating and fracturing injection grouting operation can disturb the original soil. A grouting method has been regarded as effective and developed to ameliorate the possible disturbance problem. It involves compaction grouting with low expansive pressure near the injection hole and repetitive injection and compaction with grout material that allows ideal permeating injection. This thesis develops Hybrid Grout (ie. HG grout) that allows various application in any ground condition combined together, has high fineness and low viscosity, and expands permeation injection to silty sand. It researches on the injection effect of permeable compaction grout which is done with PC packer and is a combination of HG grout and expansion agent to obtain permeation compaction effect on the area near grout injection spot by developing Permeable Compaction Type Packer(ie. PC packer). As the developed PC packer, HG grout, and and expansion agent (HI-E) are applied to reservoir embankment reinforcement grouting, possibile permeation compaction effect that satisfies reservoir embankment grouting standard is confirmed according to the research.

Pipelined Implementation of JPEG Baseline Encoder IP

  • Kim, Kyung-Hyun;Sonh, Seung-Il
    • Journal of information and communication convergence engineering
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    • v.6 no.1
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    • pp.29-33
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    • 2008
  • This paper presents the proposal and hardware design of JPEG baseline encoder. The JPEG encoder system consists of line buffer, 2-D DCT, quantization, entropy encoding, and packer. A fully pipelined scheme for JPEG encoder is adopted to speed-up an image compression. The proposed architecture was described in VHDL and synthesized in Xilinx ISE 7.1i and simulated by modelsim 6.1i. The results showed that the performance of the designed JPEG baseline encoder is higher than that demanded by real-time applications for $1024{\times}768$ image size. The designed JPEG encoder IP can be easily integrated into various application systems, such as scanner, PC camera, color FAX, and network camera, etc.