• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.61.2-61
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• 2003

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.62.3-63
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• 2003

• 광학세계
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• 통권90호
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• pp.60-65
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• 2004

현대의 정보통신 사회에 있어서 카메라는 여러 분야에 사용이 되고 있다. 카메라는 아날로그사진에서 피사체를 기록하기위한 필름을 사용하는데 이미지 센서는 빛을 변환하는 역할을 하는 필름대용품으로 사용되는 것이다. 이 이미지 센서는 전하결합소자(CCD : Charge Coupled Device)와 상보금속 산화물반도체(CMOS : Complementary Metal-Oxide-Semiconductor)가 대표적이다. 특히 디지털 카메라를 이용하여 과거의 카메

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2011년도 자성 및 자성재료 국제학술대회
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• pp.190-190
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• 2011

• 한국재료학회지
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• 제3권6호
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• pp.638-644
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• 1993

티타니움 폴리사이드 MOS(metal oxide semiconducter)캐퍼시타 구조에서 두께가 8nm인 게이트산화막의 절연파괴강도의 열화거동을 열처리조건 및 폴리실리콘막의 두께를 달리하여 조사했다. 티타니움 폴리사이드 게이트에서 게이트산화막의 전연피괴특성은 열처리 온도가 높을수록, 열처리시간이 길수록 많이 열화되어 실리사이드의 하부막인 잔류 폴리실리콘의 두께가 얇을수록 그 정도는 심해진다. 티타니움 실리사이드가 게이트산화막고 직접적인 접촉이 없더라도 게이트산화막의 신회성이 열화되는 것을 알 수 있었다. 실리사이드 형성후 열처리에 따른 게이트 산화막의 절연파괴특성열화는 티타니움 원자가 폴리실리콘을 통해 게이트산화막으로 확산되어 게이트산화막에서 티타니움의 고용량이 증가한 때문인 것이 SIMS분석 결과로부터 확인되었다.

• 한국진공학회지
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• 제10권1호
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• pp.44-50
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• 2001

전자빔증착법과 이온빔의 도움을 받는 전자빔 증착법(ion beam assisted electron beam deposition; IBAED)법으로 비정질 Si(-200nm) 박막을 p-Si 기판위에 성장하고 이 두 구조를 급속열처리산화(Rapid Thermal Oxidation; RTO)를 시킴으로서 $SiO_2$/나노결정 Si(nanocrystal Si)/p-Si구조를 형성하였다. 그 후 시료 위에 Au 막을 증착함으로서 최종적으로 나노결정이 함유된 MOS(metal-oxide-semiconductor)구조를 완성하였다. 이 MOS구조내의 나노결정 Si의 전하충전 특성을 바이어스 sweep 비율을 변화시키면서 Capacitance-Voltage(C-V) 특성을 측정하여 조사하였다. 전자빔증착시료의 경우에는 $\DeltaV_{FB}$(flatband voltage shift)가 1V 미만의 작은 C-V 이력곡선이 관측된 반면 IBAED 시료의 경우는 $\DeltaV_{FB}$가 22V(2V/s Voltage Sweep비율) 이상인 대단히 큰 C-V 이력곡선이 관측되었다. 전자빔증착중 Ar ion beam을 조사하면 표면 흡착원자이동이 활성화되고 따라서 비정질 Si내에 Si의 핵 생성율이 증가하여 후속 급속열처리산화공정중 이 높은 농도의 핵들이 나노결정 Si으로 자라나게 되고 이렇게 형성된 높은 농도의 나노결정의 전하 충전 및 방전현상이 큰 이력곡선을 나타내는 원인이라고 생각된다. 따라서 IBAED 방법이 고농도의 나노결정 Si을 형성시키는데 유용한 방법이라고 판단된다.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1220-1224
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• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.683-689
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• 2015

For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.