• The Optical Journal
• /
• s.90
• /
• pp.60-65
• /
• 2004

현대의 정보통신 사회에 있어서 카메라는 여러 분야에 사용이 되고 있다. 카메라는 아날로그사진에서 피사체를 기록하기위한 필름을 사용하는데 이미지 센서는 빛을 변환하는 역할을 하는 필름대용품으로 사용되는 것이다. 이 이미지 센서는 전하결합소자(CCD : Charge Coupled Device)와 상보금속 산화물반도체(CMOS : Complementary Metal-Oxide-Semiconductor)가 대표적이다. 특히 디지털 카메라를 이용하여 과거의 카메

• Proceedings of the Korean Magnestics Society Conference
• /
• 2011.12a
• /
• pp.190-190
• /
• 2011

• Korean Journal of Materials Research
• /
• v.3 no.6
• /
• pp.638-644
• /
• 1993

The degradation of dielectric breakdown field of 8nm-thick gate oxide ($SiO_2$) for Tipolycide MOS(meta1-oxide-semiconductor) capacitor with different annealing conditions and thickness of the polysilicon film on gate oxide was investigated. The degree of degradation in dielectric breakdown strength of the gate oxide for Ti-polycide gate became more severe with increasing annealing temperature and time, especially, for the case that thickness of the polysilicon film remained on the gate oxide after silicidation was reduced. The gate oxide degradation may be occurred by annealing although there is no direct contact of Ti-silicide with gate oxide. From SIMS analysis, it was confirmed that the degration of gate oxide during annealing was due to the diffusion of titanium atoms into the gate oxide film through polysilicon from the titanium silicide film.

• Journal of the Korean Vacuum Society
• /
• v.10 no.1
• /
• pp.44-50
• /
• 2001

Metal oxide semiconductor (MOS) structures containing nanocrystals are fabricated by using rapid thermal oxidations of amorphous silicon films. The amorphous films are deposited either by electron beam deposition method or by electron beam deposition assisted by Ar ion beam during deposition. Post oxidation of e-beam deposited film results in relatively small hysteresis of capacitance-voltage (C-V) and the flat band voltage shift, $\DeltaV_{FB}$ is less than 1V indicative of the formation of low density nanocrystals in $SiO_2$ near $SiO_2$/Si interface. By contrast, we observe very large hysteresis in C-V characteristics for oxidized ion-beam assisted e-beam deposited sample. The flat band voltage shift is larger than 22V and the hysteresis becomes even broader as increasing injection times of holes at accumulation condition and electrons at inversion condition. The result indicates the formation of slow traps in $SiO_2$ near $SiO_2$/Si interface which might be related to large density nanocrystals. Roughly estimated trap density is $1{\times}10^{13}cm^{-2}$. Such a large hysteresis may be explained in terms of the activation of adatom migration by Ar ion during deposition. The activated migration may increase nucleation rate of Si nuclei in amorphous Si matrix. During post oxidation process, nuclei grow into nanocrystals. Therefore, ion beam assistance during deposition may be very feasible for MOS structure containing nanocrystals with large density which is a basic building block for single electron memory device.

• Journal of Korean Institute of Industrial Engineers
• /
• v.29 no.2
• /
• pp.179-189
• /
• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.615-618
• /
• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1220-1224
• /
• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.28 no.11
• /
• pp.683-689
• /
• 2015

For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

• Journal of IKEEE
• /
• v.20 no.2
• /
• pp.163-166
• /
• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.204.2-204.2
• /
• 2015

산화물 반도체는 비정질임에도 불구하고 높은 이동도를 나타내며, 적은 누설 전류, 낮은 소비전력, 저온 공정 가능, 가시광선 영역에서 투명한 성질을 가지고 있다. 이와 같은 다양한 장점들로 인해 산화물 반도체를 이용한 트랜지스터는 차세대 플랫 패널 디스플레이 적용에 있어서 핵심 기술로 각광받고 있다. 한편, 소자의 크기가 점점 더 작아짐에 따라 고집적화에 따른 scaling down은 항상 언급되는 이슈이다. 이와 관련하여 소자의 높은 on current는 트랜지스터를 더 작게 구현할 수 있다는 가능성을 보여준다. 따라서 현재 소자의 on current를 높이기 위해서 소자의 구조를 변형하는 연구가 활발히 진행되고 있다. 본 연구에서는 소자의 on current를 높이기 위한 방법으로 ITO buried layer를 이용한 산화물 반도체 pseudo 트랜지스터를 제작하였다. 먼저 채널을 형성하기 전에 ITO buried layer를 형성시켜준 후, 채널 영역으로서 InGaZnO (2:1:1)를 용액 공정을 이용하여 형성시켰다. 이어서 소자의 전기적 특성 향상을 위해 마이크로웨이브 열처리를 1800 W에서 2분간 실시하였다. 또한 대조군으로 ITO buried layer를 갖지 않는 소자를 같은 방법으로 제작하여 평가하였다. 그 결과 ITO buried later를 갖는 소자에서 대조군과 비교하여 높은 on current를 나타냄을 확인하였다. 이와 같은 결과는 낮은 저항의 ITO buried layer가 current path를 제공함과 동시에 더 두꺼운 채널 층을 형성시켜 높은 on current에 기여하기 때문이다. 결과적으로 ITO buried layer를 갖는 소자 구조를 이용함으로써 고성능 트랜지스터를 제작하여 소자를 집적화 함에 있어서 유망한 소자가 될 것으로 예상된다.