• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Journal of Sensor Science and Technology
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• v.11 no.3
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• pp.163-170
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• 2002

This paper proposes a $10\;{\mu}m$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and micromachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation ($500^{\circ}C$, 1 hr at $H_2O/O_2$) and rapid thermal oxidation (RTO) process ($1050^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to $10\;{\mu}m$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 2dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about -20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Korean Journal of Materials Research
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• v.3 no.1
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• pp.19-27
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• 1993

Abstract The PZT thin film was deposited by usin. RF magnetron sputtering with PZT(52/48) target. The formation of perovskite structure PZT thin film started at 55$0^{\circ}C$ on Si substrate. The AES results showed an oxide layer formed at the between Si and PZT film during the annealing. And, Ti$O_2$ layer appeared at the between TiN and PZT film for the annealing. But, the perovskite phase PZT film was formed after the annealing on the Si$O_2$/Si substarte. The ratio in PZT film was constant across the asdeposited PZT film, but, Pb have diffused into the Si substrate and Si have out-diffused into PZT layer during the post annealing at 75$0^{\circ}C$. The dielectric constants of PZT film indicated about 1300( thickness: 1500$\AA$, at 10KHz) but, the cracks were appeared to surface for annealing.

• Applied Microscopy
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• v.45 no.4
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• pp.236-241
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• 2015

Carbon-coated Ni, Cu and Sn nanocapsules were investigated by means of X-ray diffraction (XRD), transmission electron microscopy (TEM) and a four-point probe device. All of these nanocapsules were prepared by an arc-discharge method, in which the bulk metals were evaporated under methane ($CH_4$) atmosphere. Three pure metals (Ni, Cu, Sn) were typically diverse in formation of the carbon encapsulated nanoparticles and their different mechanisms were investigated. It was indicated that a thick carbon layers formed on the surface of Ni(C) nanocapsules, whereas a thin shell of carbon with 1~2 layers covered on Cu(C) nanocapsules, and the Sn(C) nanocapsules was, in fact, a longger multi-walled carbon nanotubes partially-filled with metal Sn. As one typical magnetic/dielectric nanocomposite particles, Ni(C) nanocapsules and its counterpart of oxide-coated Ni(O) nanocapsules were compared in the electrically conductive behaviors for further applications as the electromagnetic materials.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.200-206
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• 1997

Using $SiCl_{2}H_{2}$, $NH_{3}$ and $N_{2}O$, we have fabricated silicon oxynitride ($Si_{x}O_{y}N_{z}$) layers on thermally oxidized silicon wafer by low pressure chemical vapor deposition. Three different compositions were achieved by controlling gas flow ratios($NH_{3}/N_{2}O$)) to 0.2, 0.5 and 2 with fixed gas flow of $SiCl_{2}H_{2}$. Ellipsometry and high frequency capacitance-voltage(HFCV) measurements were adapted to investigate the difference of the refractive index, dielectric constant, and composition, respectively. Regardless of nitride content, silicon oxynitrides had similar stability to silicon nitrides. The relative standing of alkali ion sensitivity in silicon oxynitride layers was influenced by nitride content. The better alkali ion-sensitivity was achieved by increasing oxide content in bulk of silicon oxynitrides.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.111-118
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• 2002

A new lithium niobate optical modulator with a polymer buffer layer on Ni in-diffused optical waveguide is proposed for the fist time, successfully fabricated and examined at a wavelength of 1.3 mm. By determining the diffusion parameters of Ni in-diffused waveguide to achieve more desirable mode size which is well matched to the mode in the fiber, the detailed results on the achievement of high optical throughput are reported. In addition, the usefulness of polymer buffer layer which can be applicable to a buffer layer in Ni in-diffused waveguide devices is demonstrated. Several sets of channel waveguides fabricated on Z-cut lithium niobate by Ni in-diffusion were obtained and on which coplanar traveling-wave type electrodes with a polymer-employed buffer layer were developed by a conventional fabrication method for characterizing of electro-optical performances of the proposed device. The experimental results show that the measured half-wave voltage is of ~10 V and the total measured fiber-to-fiber insertion loss is of ~6.4 dB for a 40 mm long at a wavelength of =1.3 mm, respectively. From the experimental results, it is confirmed that the polymer-employed buffer layer in LiNbO3 optical modulator can be a substitute material instead of silicon oxide layer which is usually processed at a high temperature of over $300^{\circ}C$. Moreover, the fabrication tolerances by using polymer materials in LiNbO3 optical modulators are much less strict in comparison to the case of dielectric buffer layer.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.791-796
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• 2017

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

• Transactions on Electrical and Electronic Materials
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• v.12 no.2
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• pp.72-75
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• 2011

In this study, $(K_{0.5}Na_{0.5})(Nb_{0.97}Sb_{0.03})O_3+0.9$ mol% $K_{5.4}Cu_{1.3}Ta_{10}O_{29}+x$ mol% $K_4CuNb_8O_{23}$ (x = 0, 0.2, 0.6, 0.8) ceramics were prepared by a conventional mixed oxide method. Their microstructure and electric properties were investigated. The secondary phase was made by virtue of $K_4CuNb_8O_{23}$ (KCN) addition in the $(K_{0.5}Na_{0.5})(Nb_{0.97}Sb_{0.03})O_3$ system ceramics. However, the sinterability of the ceramics increased with increasing $K_4CuNb_8O_{23}$ content. At the 0.6 mol% $K_4CuNb_8O_{23}$ added composition ceramics sintered at $1,060^{\circ}C$, kp and $d_{33}$ showed the optimum values of 0.39 and 145 pC/N, respectively, suitable for piezoelectric actuator application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.198-203
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• 2012

In this study, $[Li_{0.04}(Na_{0.5}K_{0.5})_{0.96}](Nb_{0.86}Ta_{0.10}Sb_{0.04})O_3+xSrO$ (x=0, 0.0025, 0.005, 0.0075) ceramics were synthesized by the conventional mixed oxide method. The X-ray diffraction patterns demonstrated that ceramics possessed single perovskite structure. The SEM images indicate that microstructure can be obviously affected by a small amount of added SrO. The phase transition temperature tetragonal-cubic($T_c$) and orthorhombic-tetragonal($T_{o-t}$) shifts downward and upward with the increase of Sr addition, respectively. The excellent piezoelectric properties of $d_{33}=170[pC/N]$, $k_p=0.37$, $Q_m=64.12$, $T_{o-t}=153^{\circ}C$ and $T_c=370^{\circ}C$ were obtained from the 0.25 mol% Sr added ceramics sintered at $1,120^{\circ}C$ for 1 h.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.470-470
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• 2013

Recently, active materials such as amorphous silicon (a-Si), poly crystalline silicon (poly-Si), transition metal oxide semiconductors (TMO), and organic semiconductors have been demonstrated for flexible electronics. In order to apply flexible devices on the polymer substrates, all layers should require the characteristic of flexibility as well as the low temperature process. Especially, pentacene thin film transistors (TFTs) have been investigated for probable use in low-cost, large-area, flexible electronic applications such as radio frequency identification (RFID) tags, smart cards, display backplane driver circuits, and sensors. Since pentacene TFTs were studied, their electrical characteristics with varying single variable such as strain, humidity, and temperature have been reported by various groups, which must preferentially be performed in the flexible electronics. For example, the channel mobility of pentacene organic TFTs mainly led to change in device performance under mechanical deformation. While some electrical characteristics like carrier mobility and concentration of organic TFTs were significantly changed at the different temperature. However, there is no study concerning multivariable. Devices actually worked in many different kinds of the environment such as thermal, light, mechanical bending, humidity and various gases. For commercialization, not fewer than two variables of mechanism analysis have to be investigated. Analyzing the phenomenon of shifted characteristics under the change of multivariable may be able to be the importance with developing improved dielectric and encapsulation layer materials. In this study, we have fabricated flexible pentacene TFTs on polymer substrates and observed electrical characteristics of pentacene TFTs exposed to tensile and compressive strains at the different values of temperature like room temperature (RT), 40, 50, $60^{\circ}C$. Effects of bending and heating on the device performance of pentacene TFT will be discussed in detail.