• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.707-710
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• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). In this paper, we have investigated slurry properties and CMP performance of silicon dioxide (oxide) as a function of different temperature of slurry. Thermal effects on the silica slurry properties such as pH, particle size, conductivity and zeta potential were studied. Moreover, the relationship between the removal rate (RR) with WIWNU and slurry properties caused by changes of temperature were investigated. Therefore, the understanding of these temperature effects provides a foundation to optimize an oxide CMP Process for ULSI multi-level interconnection technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.120-124
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• 2004

본 연구는 Diluted Ceria 입자를 사용한 $SiO_2$(Oxide) CMP 현상에 대한 내용이다. Ceria Slurry의 경우 Silica Slurry와 비교하였을 때 Oxide Wafer 표면과 축합 화학반응을 일으키며 Chemistry Dominant한 CMP Mechanism을 따르고, Wafer Center Removal Rate(RR) Fast 의 특성을 가진다. Ceria Slurry의 문제점인 연마 불균일도를 해결하기 위해 Tribological System을 이용하였다. CMP Tribology는 Pad-Slurry 유막-Wafer의 System을 가지며 윤활막에 작용하는 마찰계수(COF)가 주요 인자이다. Tribology에 적용되는 Stribeck Curve를 통해 Slurry 윤활막의 두께(h) 정도를 예상할 수 있으며, 이 윤활막의 두께를 조절함으로써 Uniformity 향상이 가능하다. 이 Ceria Slurry CMP의 연마 불균일도를 향상시킬 수 있는 방법으로 pH 조절 및 점도 증가가 있다. Ceria 입자 CMP는 분산액의 pH 변화에 강한 작용을 받게 되며 PH5 근방에서 최적화된 Uniformity가 가능하다. 점도를 증가시키는 경우 유막 h가 증가하게 되어 Ceria Slurry의 유동이 균일 분포 상태에 가까워지며 Wafer Uniformity 향상이 가능하다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.171-174
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• 2000

We have investigated the CMP slurry properties of silicate oxide thin films surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-ortho-silicate glass(PE-TEOS), $O_3$ boro-phospho silicate giass( $O_3$-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray Fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing, which is due to a CMP slurry. The polished $O_3$-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.443-444
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• 2008

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.8
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• pp.44-50
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• 2019

CMP is the most critical process in the manufacture of silicon wafers, and the use of retaining rings, which are consumable parts used in CMP equipment, is increasingly important. Since the retaining ring is made of plastic, it is not only weak in strength but also has the problem of taking a long time for the flattening operation of the ring itself performed before the CMP process, and of the imbalance of force due to bolt tightening causing uneven wear. In order to solve this problem, the retaining ring and the insert ring are integrally used, and the flatness of the retaining ring may be affected depending on the material of the insert ring. Also, the residual stress generated in the manufacturing process of the insert ring may cause distortion of the ring, which may adversely affect the precision polishing. In this study, when the insert ring is made of Zn or STS304, the thickness variation and the flatness of the retaining ring are compared and, finally, the material removal rate is analyzed by polishing the wafer by the oxide CMP process. Through these experiments, the effects of the insert ring material on the polishing accuracy of the wafers were investigated.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.723-725
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• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.235-239
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• 2001

In recent years, as Chemical Mechanical Planarization(CMP) has been routinely utilized in integrated circuit(IC) fabrication, the consumption of slurry, main consumable in a CMP process, is greatly increased. Thus the reprocess of CMP slurries has been actively considered in the industry to reduce cost-of-consumable (COC). The main purpose of this study was to recycle the used oxide slurry using filters as a new method. As a result, Ultra Fine(UF) Filter could distinguish silica from the used oxide slurry and Reverse Osmosis(RO) Filter could distinguish Deionized(DI) Water and chemistry from chemistry solution. The tetraethylorthosilicate removal rate was almost the same as the number of recycle polishing was increased, when it was modified by slightly adding new SS-12 slurry. The microscratch didnt found as the number of recycle polishing was increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.378-379
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.567-568
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• 2006

To investigate the recycle possibility of slurry for the oxide-chemical mechanical polishing (oxide-CMP) application, three kinds of retreated methods were introduced as follows: First, the effects on the addition of silica abrasives and the diluted silica slurry (DSS) on CMP performances were investigated. Second, the characteristics of mixed abrasive slurry (MAS) using non-annealed and annealed alumina ($Al_2O_3$) powder as an abrasive added within DSS were evaluated to achieve the improvement of removal rates (RRs) and within-wafer non-uniformity (WIWNU%). Third, the oxide-CMP wastewater was examined in order to evaluate the possible ways of reusing it. And then, we have discussed the CMP characteristics of silica slurry retreated by mixing of original slurry and used slurry (MOS).

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.