• 제목/요약/키워드: Output voltage ripple

검색결과 373건 처리시간 0.02초

입력전류와 커패시터 전압의 맥동저감을 위한 개선된 LCCT Z-소스 DC-AC 인버터 (Improved LCCT Z-Source DC-AC Inverter for Ripple Reduction of Input Current and Capacitor Voltage)

  • 신연수;정영국;임영철
    • 전기학회논문지
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    • 제61권10호
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    • pp.1432-1441
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    • 2012
  • In this study, an improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source inverter(Improved LCCT ZSI) with characteristics of Quasi Z-source inverter(QZSI) and LCCT Z-source inverter(LCCT ZSI) is proposed. The proposed inverter can also reduce the voltage stress and input current/capacitor voltage ripples compared with conventional LCCT ZSI and Quasi ZSI. A two winding trans in Z-impedance network of the conventional LCCT ZSI is replaced by a three winding trans in the proposed inverter. To verify the validity of the proposed inverter, a DSP controlled hardware was made and PSIM simulation was executed for each method. Comparing the current and voltage ripples of each method under the condition of input DC voltage 70[V] and output AC voltage 76[Vrms], the input current and capacitor voltage ripple factors of the proposed inverter were low as 11[%] and 1.4[%] respectively. And, for generation of the same output AC voltage of each method, voltage stress of the proposed inverter was low as 175[V] under the condition of duty ratio D=0.15. As mentioned above, we could know that the proposed inverter have the characteristics of low voltage stress, low ripple factor and low operation duty ratio compared with the conventional methods. Finally, the efficiency according to load change/duty ratio and the transient state characteristics were discussed.

LED 정전류 구동회로의 입력전압 리플 크기에 의한 특성 비교 (Characteristic comparisons of the constant current LED driver by the ripple of the input voltage)

  • 박종연;전인웅;유진완;최영민
    • 산업기술연구
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    • 제32권A호
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    • pp.115-118
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    • 2012
  • Recently, there are a lot of papers in order to replace the electrolytic capacitor into the film capacitor in output of PFC(Power Factor Correction). However, the film capacitor, which has capacitance of low values, causes a large ripple voltage in output of PFC. The LED drivers are connected series in the output of PFC and affected by the magnitude of voltage ripple. In this paper, we have compared the fixed frequency method with the variable frequency for the constant-current control and propose the control method to avoid the sub-harmonic oscillation in the variable input voltage. An 80W PFC, using film capacitors instead of electrolytic capacitors, and LED driver has been built and compared the fixed frequency control method with the variable frequency control method.

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4스위치 3상 인버터의 직류 링크 중성점 전압 추정에 의한 출력전압 불평형 개선 (Improvement of Output Voltage Waveforms by DC-Link Neutral Point Voltage Estimation for FSTPI)

  • 김정훈;조인철;이홍희
    • 전기학회논문지
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    • 제58권9호
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    • pp.1741-1749
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    • 2009
  • It is very important to maintain the balanced output voltage waveforms under the unbalanced DC-link voltages in the four-switch three-phase inverter(FSTPI). In this paper, the improvement of output voltage waveforms is proposed with the aid of DC-link voltage ripple estimation. The proposed method can be implemented without the additional voltage sensor. The proposed method applied to the permanent magnet synchronous motor (PMSM) is simulated and experimented in order to verify its feasibility.

Analysis, Design and Implementation of a Soft Switching DC/DC Converter

  • Lin, Bor-Ren
    • Journal of Power Electronics
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    • 제13권1호
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    • pp.20-30
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    • 2013
  • This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

출력 전압 맥동감소를 위한 직렬공진형 변환기의 제어기 설계 (Controller Design of the Series Resonant Converter for Reducing Output Voltage Ripple)

  • 김만고;한재원;윤명중
    • 대한전기학회논문지
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    • 제37권6호
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    • pp.376-382
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    • 1988
  • A small-signal low-frequency disturbance of the input line affects the regulated-output voltage of the series resonant converter. To mitigate the detrimental effect, the output feedback PI-controller is employed. Small-signal linear models are represented to characterize the closed loop series resonant converter system. Design equations for the PI-controller which satisfy stability and percent ripple conditions are derived from the closed-loop linear model. Experimental results are presented which show excellent correlation with theory.

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인터리브드 소프트 스위칭 부스트 컨버터의 입출력 리플 분석 (Input/Output Ripple Analysis of Interleaved Soft Switching Boost Converter)

  • 정두용;지용혁;김영렬;정용채;원충연
    • 전력전자학회논문지
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    • 제17권2호
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    • pp.182-189
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    • 2012
  • In this paper, the input current and output voltage ripple of the soft switching interleaved boost converter was analyzed. Ripples of input current and output voltage with an interleaved method is analysed and as a result, the facts that it has lower ripple current than conventional interleaved method is verified. it means that a capacity of a main inductor can be reduced. Besides, a low capacitance of capacitor which means high lifetime and confidence can be used because of reducing ripples of output voltage. In order to verify the validity of the proposed converter used 10uF film capacitor, experiment was performed, and the efficiency of the proposed converter was measured with variable load and duty conditions.

QSRC의 출력전압맥동해석 (Output Voltage Ripple Analysis of Quantum Series Resonant Converter)

  • 임성운;권우현;조규형
    • 전자공학회논문지B
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    • 제31B권3호
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    • pp.141-149
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    • 1994
  • In this paper, we could find optimum quantum sequence(OQS) to minimize the output ripple voltage of the quantum series resonant converter(QSRC). This sequence control is so general that it is irrelevant to the voltage gain so far as it is operating in the continuous conduction mode(CCM). Further more the dynamic range of QSRC is much extended by the optimum quantum sequence control(OQSC). Througuout the time-domain analysis, the solution of steady state and the boundary condition between continuous and discontinuous mode is QSRC is obtained. This feature is verified by simulations and experiments with good agreements.

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단위 역률을 갖는 3상 BUCK 다이오드 정류기에서의 DC 리플-전압 저감 (DC Ripple-Voltage Suppression in three Phase BUCK DIODE Rectifiers with Unity Power Factor)

  • 이동윤;송중호;최주엽;최익;김광배;현동석
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 F
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    • pp.2653-2655
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    • 1999
  • A technique to suppress the low frequency ripple voltage of the DC output voltage in three-phase buck diode rectifiers is presented. A pulse frequency modulation method is employed to regulate the output voltage of the rectifier and guarantee zero-current switching of the switch over the wide operating range. The pulse frequency control method used in this paper shows generally good performance such as low THD of the input line current and unity power factor. In addition, the pulse frequency method can be effectively used to suppress the low frequency voltage ripple appeared in the dc output voltage. The proposed technique illustrates its validity and effectiveness through the respective simulations and experiments.

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연료전지용 다상부스트 컨버터의 최적 설계기법 (Optimal Design of Interleaved Boost Converters for Fuel Cell Applications)

  • 최규영;김종수;강현수;이병국
    • 전기학회논문지
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    • 제57권6호
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    • pp.1003-1011
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    • 2008
  • In this paper, optimal design of interleaved boost converters is studied in order to design low ripple, size, loss and high performance converters for fuel cell applications. Also, the process of optimal design of interleaved boost converter has been performed. Input current ripple, output voltage ripple, losses and capacity of electrical components are theoretically analyzed and informative simulation and experimental results are provided.

Zero-Voltage and Zero-Current-Switching (ZVZCS) Full Bridge PWM Converter with Zero Current Ripple

  • Baek, J.-W.;Cho, J.G.;Jeong, C.Y.;Yoo, D.W.
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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    • pp.79-84
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    • 1998
  • A novel zero voltage and zero current switching (ZVZCS) full bridge (FB) PWM converter with low output current ripple is presented. A simple auxiliary circuit added in the secondary provides ZVZCS conditions to primary switches, ZVS for leading-leg switches and ZCS for lagging-leg switches, as well as reduces the output current ripple (ideally zero ripple). The auxiliary circuit includes neither lossy components nor additional active switches which are demerits of the previously presented ZVZCS converters. Many advantages including simple circuit topology, high efficiency, low cost and low current ripple make the new converter attractive for high performance high power (>1kW) applications. The principle of operation, features and design considerations are illustrated and verified on a 2.5kW, 100KHz IGBT based experimental circuit.

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