• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.6
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• pp.767-775
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• 2018

To develop and check a Radar Processor Unit, checking the function and performance of the requirement is very important factor in developing Radar. General methods for verifying the Radar is simulation test, environment linkage test and field operation test, firstly, in case of requirement analysis phase, verify Radar algorithm and design by using mathematical method based simulation test method, and secondly, in case of unit test and integrated test phase, Test Equipment is set to simulate radar environment in the lab to verify radar function and performance. Lastly, field operation test phase is carried out to confirm the function and performance after it is mounted on the actual equipment. To successfully develop Radar Processor Unit, using the method of field operation test method after sufficient test cases are tested in radar environmental interlocking method in order to save cost and testing period and because of this reason, development of the Radar Processor Unit Test Equipment is becoming very important factor. In this paper, we introduce the concept of test equipment development and important factors in test equipment, which are target simulation, data processing and device interlocking.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.341-344
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• 2000

The 0-1 knapsack processor performing dynamic programming is designed and implemented on a programmable logic device. Three types of a processor, each with different behavioral models, are presented, and the operation of a processor of each type is verified with an instance of the 0-1 knapsack problem.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• ETRI Journal
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• v.31 no.6
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• pp.709-716
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• 2009

In this paper, we propose a novel reconfigurable processor using dynamically partitioned single-instruction multiple-data (DP-SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P-SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD-based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P-SIMD, and DP-SIMD. Experimental results show that the DP-SIMD control method is more efficient than SIMD and P-SIMD control methods by about 15% and 14%, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• Journal of Hydrogen and New Energy
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• v.27 no.5
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• pp.485-493
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• 2016

Recently submarine and unmanned underwater vehicle (UUV) are equipped with a fuel cell system as an air independent propulsion system. Methanol fuel processor can efficiently supply the hydrogen to the fuel cell system to improve the ability to dive. This study investigated the optimal conditions of the methanol fuel processor that may be used in the closed environment. For this purpose, the numerical model based on Gibbs minimization equation was established for steam reformer and three exhaust gas burners. After simulating the characteristics of steam reformer according to the steam-to-carbon ratio (SCR) and the pressure change, the SCR condition was able to narrow down to 1.1 to 1.5. Considering water consumption and the amount of heat recovered from three burners, the optimum condition of the SCR can be determined to be 1.5. Nevertheless, the additional heat supply is required to satisfy the heat balance of the methanol fuel processor in the SCR=1.5. In other to obtain additional amount of heat, the combustion of methanol is better than the increased of SCR in terms of system design.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1991.04a
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• pp.243-250
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• 1991

This paper concerns the development of NC programming system TIG (Turning with Interactive Graphics) with interactive graphics for turning operation. The system cosists of the processor, the post-processor and the system-user interface. Different from previous segment contour based NC graphic programming systems, the frliability and efficiencyof programming is realized by using Boolean operation with block unit based ICONs for the geometry definition. The tool motion can be also displayed on the screen together with the part contour. The system calculate automatically the number of passes based on the user specified cutting conditions.

• International Journal of Precision Engineering and Manufacturing
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• v.2 no.3
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• pp.69-78
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• 2001

This paper presents a process and operation planning system and an NC code post-processor for effective machining of press dies for production of cars. Based on the machining feature, major parts of press dies are categorized into 15 groups and a standard process plan is defined for each group. The standard process plan consists of a series of processes where a process is defined as a group of operations that can be done with one setup. Details such as cutting tools, cutting conditions, and tool paths are decided at the operation planning stage. At the final stage of process and operation planning, the NC code post-processor adjusts feedrates along the tool path to reduce machining time while maintaining the quality. The adjustment rule is selected based on the machining load estimated by virtual machining.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.94-100
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• 1999

This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

• Journal of Electrical Engineering and Technology
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• v.3 no.2
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• pp.243-253
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• 2008

This paper deals with the analysis, design, and implementation of a single phase AC-DC Zeta converter with high frequency transformer isolation and power factor correction(PFC) in two modes of operation, discontinuous current mode of operation(DCM), and continuous current mode of operation(CCM). A Digital Signal Processor(DSP) based implementation is carried out for validation of the Zeta converter developed design in discontinuous mode of operation. A comparison of both modes of operation is presented for a 1kW power rating from the point of view of steady state and dynamic behavior, power quality, simplicity, control technique, device rating, and converter size. The experimental results of a developed prototype of Zeta converter are presented for validation of the developed design. It is observed that CCM is most suitable for higher power applications where it requires some complex control and sensing of the additional variables.