• Title/Summary/Keyword: OneNAND 플래시 메모리

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Improving the Read Performance of OneNAND Flash Memory using Virtual I/O Segment (가상 I/O 세그먼트를 이용한 OneNAND 플래시 메모리의 읽기 성능 향상 기법)

  • Hyun, Seung-Hwan;Koh, Kern
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.7
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    • pp.636-645
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    • 2008
  • OneNAND flash is a high-performance hybrid flash memory that combines the advantages of both NAND flash and NOR flash. OneNAND flash has not only all virtues of NAND flash but also greatly enhanced read performance which is considered as a downside of NAND flash. As a result, it is widely used in mobile applications such as mobile phones, digital cameras, PMP, and portable game players. However, most of the general purpose operating systems, such as Linux, can not exploit the read performance of OneNAND flash because of the restrictions imposed by their virtual memory system and block I/O architecture. In order to solve that problem, we suggest a new approach called virtual I/O segment. By using virtual I/O segment, the superior read performance of OneNAND flash can be exploited without modifying the existing block I/O architecture and MTD subsystem. Experiments by implementations show that this approach can reduce read latency of OneNAND flash as much as 54%.

A Practical XIP Scheme using the Memory Management of Time Measuring at OneNAND Flash (원낸드 플래시 메모리에서 시간계측메모리관리를 이용한 XIP 활용 기법)

  • Sang ho Cho;Taehyoung Kim;Moon Jeong Kim;Young Ik Eom
    • Proceedings of the Korea Information Processing Society Conference
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    • 2008.11a
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    • pp.885-888
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    • 2008
  • 낸드(NAND) 플래시 메모리와 노어(NOR) 플래시 메모리의 장점을 결합시킨 원낸드(OneNAND) 플래시 메모리가 개발되면서 메모리의 시장에 큰 변화가 왔다. 그러나 기존의 낸드 플래시 메모리에서 사용되던 메모리 관리 기법이 그대로 원낸드 플래시 메모리에서 사용됨에 따라 원낸드 플래시 메모리만의 장점을 활용하지 못하고 있다. 본 논문에서는 기존의 메모리 관리 기법을 원낸드 플래시 메모리에 적합한 형태로 개선하였다. 제안 기법은 XIP 기능과 새로운 버퍼 관리 방법을 활용하여 원낸드 플래시 메모리의 성능을 최대한 이끌어 낸다. 그 결과 시스템의 전체적인 수행속도를 향상시킬 수 있었다.

Efficient FTL Mapping Management for Multiple Sector Size-based Storage Systems with NAND Flash Memory (다중 섹터 사이즈를 지원하는 낸드 플래시 메모리 기반의 저장장치를 위한 효율적인 FTL 매핑 관리 기법)

  • Lim, Seung-Ho;Choi, Min
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.12
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    • pp.1199-1203
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    • 2010
  • Data transfer between host system and storage device is based on the data unit called sector, which can be varied depending on computer systems. If NAND flash memory is used as a storage device, the variant sector size can affect storage system performance since its operation is much related to sector size and page size. In this paper, we propose an efficient FTL mapping management scheme to support multiple sector size within one NAND flash memory based storage device, and analyze the performance effect and management overhead. According to the proposed scheme, the management overhead of proposed FTL management is lower than conventional scheme when various sector sizes are configured in computer systems, while performance is less degraded in comparison with single sector size support system.

Design and Performance Evaluation of a Flash Compression Layer for NAND-type Flash Memory Systems (NAND형 플래시메모리를 위한 플래시 압축 계층의 설계 및 성능평가)

  • Yim Keun Soo;Bahn Hyokyung;Koh Kern
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.4
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    • pp.177-185
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    • 2005
  • NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

A method for optimizing lifetime prediction of a storage device using the frequency of occurrence of defects in NAND flash memory (낸드 플래시 메모리의 불량 발생빈도를 이용한 저장장치의 수명 예측 최적화 방법)

  • Lee, Hyun-Seob
    • Journal of Internet of Things and Convergence
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    • v.7 no.4
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    • pp.9-14
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    • 2021
  • In computing systems that require high reliability, the method of predicting the lifetime of a storage device is one of the important factors for system management because it can maximize usability as well as data protection. The life of a solid state drive (SSD) that has recently been used as a storage device in several storage systems is linked to the life of the NAND flash memory that constitutes it. Therefore, in a storage system configured using an SSD, a method of accurately and efficiently predicting the lifespan of a NAND flash memory is required. In this paper, a method for optimizing the lifetime prediction of a flash memory-based storage device using the frequency of NAND flash memory failure is proposed. For this, we design a cost matrix to collect the frequency of defects that occur when processing data in units of Drive Writes Per Day (DWPD). In addition, a method of predicting the remaining cost to the slope where the life-long finish occurs using the Gradient Descent method is proposed. Finally, we proved the excellence of the proposed idea when any defect occurs with simulation.

Worst Case Response Time Analysis for Demand Paging on Flash Memory (플래시 메모리를 사용하는 demand paging 환경에서의 태스크 최악 응답 시간 분석)

  • Lee, Young-Ho;Lim, Sung-Soo
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.6 s.44
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    • pp.113-123
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    • 2006
  • Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.

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Erase Group Flash Translation Layer for Multi Block Erase of Fusion Flash Memory (퓨전 플래시 메모리의 다중 블록 삭제를 위한 Erase Croup Flash Translation Layer)

  • Lee, Dong-Hwan;Cho, Won-Hee;Kim, Deok-Hwan
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.46 no.4
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    • pp.21-30
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    • 2009
  • Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

A Secure Deletion Method for NAND Flash File System (NAND 플래시 파일 시스템을 위한 안전 삭제 기법)

  • Lee, Jae-Heung;Oh, Jin-Ha;Kim, Seok-Hyun;Yi, Sang-Ho;Heo, Jun-Young;Cho, Yoo-Kun;Hong, Ji-Man
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.3
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    • pp.251-255
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    • 2008
  • In most file systems, if a file is deleted, only the metadata of the file is deleted or modified and the file's data is still stored on the physical media. Some users require that deleted files no longer be accessible. This requirement is more important in embedded systems that employ flash memory as a storage medium. In this paper, we propose a secure deletion method for NAND flash file system and apply the method to YAFFS. Our method uses encryption to delete files and forces all keys of a specific file to be stored in the same block. Therefore, only one erase operation is required to securely delete a file. Our simulation results show that the amortized number of block erases is smaller than the simple encryption method. Even though we apply our method only to the YAFFS, our method can be easily applied to other NAND flash file systems.

Log-Structured B-Tree for NAND Flash Memory (NAND 플래시 메모리를 위한 로그 기반의 B-트리)

  • Kim, Bo-Kyeong;Joo, Young-Do;Lee, Dong-Ho
    • The KIPS Transactions:PartD
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    • v.15D no.6
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    • pp.755-766
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    • 2008
  • Recently, NAND flash memory is becoming into the spotlight as a next-generation storage device because of its small size, fast speed, low power consumption, and etc. compared to the hard disk. However, due to the distinct characteristics such as erase-before-write architecture, asymmetric operation speed and unit, disk-based systems and applications may result in severe performance degradation when directly implementing them on NAND flash memory. Especially when a B-tree is implemented on NAND flash memory, intensive overwrite operations may be caused by record inserting, deleting, and reorganizing. These may result in severe performance degradation. Although ${\mu}$-tree has been proposed in order to overcome this problem, it suffers from frequent node split and rapid increment of its height. In this paper, we propose Log-Structured B-Tree(LSB-Tree) where the corresponding log node to a leaf node is allocated for update operation and then the modified data in the log node is stored at only one write operation. LSB-tree reduces additional write operations by deferring the change of parent nodes. Also, it reduces the write operation by switching a log node to a new leaf node when inserting the data sequentially by the key order. Finally, we show that LSB-tree yields a better performance on NAND flash memory by comparing it to ${\mu}$-tree through various experiments.

Characterizing the Tail Distribution of Android IO Workload (안드로이드 입출력 부하의 꼬리분포 특성분석)

  • Park, Changhyun;Won, Youjip;Park, Yongjun
    • KIPS Transactions on Computer and Communication Systems
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    • v.8 no.10
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    • pp.245-250
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    • 2019
  • The use of NAND flash memory has increased rapidly due to the development of mobile fields. However, NAND flash memory has a limited lifespan, so studies are underway to predict its lifespan. Workload is one of the factors that significantly affect the life of NAND flash memory, and workload analysis studies in mobile environments are insufficient. In this paper, we analyze the distribution of workload in the mobile environment by collecting traces generated by using Android-based smartphones. The collected traces can be divided into three groups of hotness. Also they are distributed in the form of heavy tails. We fit this to the Pareto, Lognormal, and Weibull distributions, and Traces are closest to the Pareto distribution.