• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1109-1112
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• 1999

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.181-186
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• 1999

For an unmanned machining system, the control and disposal of chips is one of the most serious problems at present. In order to perform chip control, feed/land length($F_L$) was introduced, and using this parameter, the cutting performance and chip breaking characteristics of groove-type and the land -angle-type chip formers were assessed. The specific cutting energy consumed and the shape of broken chips with its breaking cycle time were evaluated to find out the ranges of $F_L$ value where efficient cutting and effective chip breaking could be achieved. The C type chip was found to be the most preferable from the view point of cutting efficiency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.19-28
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• 1997

This paper presents the design of an SSIC chip for synchronization between main and sub pictures in the multi channel TV system (MUCTS). This chip can resolve problems in MUCTS, such as passing through and vertical jolt phenomena. In addition, this chip rpvivides compatibility for normal/doulble scan, interlace/progressive and normal (4:3)/wide (16:9) systems and has high hjorizontal and vertical resolutions (340) dots and 150 lines). In each mode there are 1 channel, 3 channel, and 4 position display functions. This MUCTS chip including three A/D coverters, a D/A converter and seven line memories was fabricated with one chip by using the $0.8\mu\textrm{m}$ CMOS technology. The application areas of this MUCTS ASIC chip include the wide TV, projection TV and te next generation TV for the DBS (direct broadcast system).

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.2
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• pp.73-80
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• 2006

This paper describes a analysis on the chip thickness model required for cutting force simulation in ball-end milling. In milling, cutting forces are obtained by multiplying chip area to specific cutting forces in each cutting instance. Specific cutting forces are one of the important factors for cutting force predication and have unique value according to workpiece materials. Chip area in two dimensional cutting is simply calculated using depth of cut and feed, but not simply obtained in three dimensional cutting such as milling due to complex cutting mechanics. In ball-end milling, machining is almost performed in the ball part of the cutter and tool radius is varied along contact point of the cutter and workpiece. In result, the cutting speed and the effective helix angle are changed according to length from the tool tip. In this study, for chip thickness model analysis, tool and chip geometry are analyzed and then the definition of chip thickness and estimation method are described. The resulted of analysis are verified by compared with geometrical simulation and other research. The proposed chip thickness model is more precise.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.2
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• pp.97-104
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• 2011

This paper deals with the quick and precise disaster prevention automation system (DPAS) based on information communication technology (IT) that detects fire and disasters in the building automatically and quickly and then activates the facilities to extinguish fire and disasters, monitoring such situation in a real time through wire-wireless communication network. The proposed DPAS is applied a programmable logic controller (PLC) of one-chip type which is smallsize and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLC analyzes detected signals from sensors in a case of fire and disasters, then activates fire extinguishing facilities for rapid suppression. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication. The transferred data sounds an emergency alarm signal, and operates a monitoring program. The proposed DPAS based on IT will minimize the life and wealth loss from rapid measures while prevents fire and disasters.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.101-106
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• 2001

In order to establish the optimum process parameters and diamond saw blade composition for machining natural stone, the chip formation process and the wear process must be understood. Diamond saw blade is one of the most effective, versatile, and extensively used methods of processing rock and other hard materials, such as granite, marble, concrete and asphalt. For many years, it has been known that chip thickness is one of the most significant in the understanding of the sawing process, and other variables such as force and power have been correlated with it. In this study, mathematical relations of a material chipped by a single grit of the saw blade will be undertaken. The material chipping geometries have been mathematically defined and derived as maximum chip thickness.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.191-197
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• 2005

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.3-10
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• 1986

In this paper, a scanconverter which displays the biological signals of low frequency on CRT for the purpose of easy read-out is attempted to design for using the CRTC, and it stows some good effectivenesses The results obtained in this experiment are as follows : (1) Using only one chip, CRT controller, it can display both waveforms and characters simultaneously. (2) The flexibility of CPU program can be obtained using the sub-microproce ssor function of CRTC chip. (3) The trend of digital data is possible through the graphic function (4) The vibration of displayed waveform can be prevented using the chip simplification and the trigger signal of one chip. (5) Operation with microprocessor malies the expansion and interface easy.