• 제목/요약/키워드: One-chip

검색결과 1,243건 처리시간 0.027초

COG(Chip On Glass)를 위한 ACA (Anisotropic Conductive Adhesives) 공정 조건에 관한 연구 (A Study on the Process Conditions of ACA( Anisotropic Conductance Adhesives) for COG ( Chip On Glass))

  • 한정인
    • 한국재료학회지
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    • 제5권8호
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    • pp.929-935
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    • 1995
  • 구동 IC를 유리기판 위의 Al패드 전극에 연결하는 LCD(Liquid Crystal Display) 모듈을 실장하는 Chip On Glass (COG) 기술을 개발하기 위하여 기존에 잘 알려진 기술 가운데 실제로 적용 가능성이 가장 유망한 이방성 도전 접착제 (ACA, Anisotropic Conductive Adhesives)를 사용한 공정에 대하여 조사하였다. ACA 공정은 본딩 부분에 ACA 수지를 균일하게 분포시키는 공정과 자외선을 조사하여 수지를 경화하여 칩을 실장하는 공정의 2단계로 진행하였다. 칩에 가해준 하중은 2-15kg이었고 칩의 예열 온도는 12$0^{\circ}C$이었다. 이방성 도전체는 Au 또는 Ni이 표면 피막 재료로 사용된 것을 사웅하였으며 전도성 입자의 갯수가 500, 1000, 2000, 4000개/$\textrm{mm}^2$이며 크기가 5, 7, 12$\mu\textrm{m}$이었다. ACA 처리의 결과 입자 크기가 5$\mu\textrm{m}$이고 입자 밀도는 4000개/$\textrm{mm}^2$일 경우가 대단히 낮은 접촉 저항 및 가장 안정된 본딩 특성을 나타냈었다.

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Smart grid and nuclear power plant security by integrating cryptographic hardware chip

  • Kumar, Niraj;Mishra, Vishnu Mohan;Kumar, Adesh
    • Nuclear Engineering and Technology
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    • 제53권10호
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    • pp.3327-3334
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    • 2021
  • Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

GHz 대역을 위한 1005 RF 칩 인덕터의 최적 구조 설계 (The Optimum Structure Design of 1005 RF Chip Inductors for GHz Band)

  • 김재욱;유창근
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.785-788
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    • 2005
  • In this study, micro-scale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was $1.0{\times}0.5{\times}0.5mm^3$ The material and shape of the core were 96% $Al_2O_3$ and I-type. The material and number of turn of coil were copper (Cu) and 6. The diameter ($40{\mu}m$) of coil and length (0.35mm) of solenoid were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. High frequency characteristics of the inductance (L) and quality-factor (Q) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 10.8nH and quality factors of 25.2 at 250MHz, and show results comparable to those measured for the inductors prepared by CoilCraftTm that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the Land Q of the inductors developed well.

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ESC 공정으로 제작된 금형강의 가공특성연구 (Machining Characteristics of Tool Steels Manufactured by Electro Slag Casting Process)

  • 김정운;김봉준;이득우;문영훈
    • 대한기계학회논문집A
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    • 제26권6호
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    • pp.1120-1126
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    • 2002
  • Machining characteristics of tool steels manufactured by electro slag casting process has been investigated in this study. For the estimation of machinability, turning and drilling tests are carried out. The chip shapes at various velocities are investigated for the comparison of turning workabilities of tool steels because the chip shapes reflect characteristics of cutting resistance. In case of drilling test, feed motor currents measured by a hall sensor are used as a measure for the drilling resistance. The machining characteristics of the tool steels are strongly correlated with tensile properties, such as tensile strength, hardness, and ductility. In case of turning workability, it was found to be favoured by the higher tensile strength, while the opposite is true far the drilling workability. The electro-slag casted materials show better turning workability in the viewpoint of chip shapes and, the quenching-tempered electro-slag casted material has relatively better drilling machinability than that of the annealed one.

Micro EDM을 이용한 Lab-on-a-chip금형의 미세 패턴 제작에 관한 연구 (A Study on the Micro Pattern Fabrication of Lab-on-a-chip Mold Master using Micro EDM)

  • 신봉철;김규복;조명우;김보현;정우철;허영무
    • 소성∙가공
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    • 제20권1호
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    • pp.17-22
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    • 2011
  • Recently, analyzing system is studying for applying to biomedical engineering field, actively. Micro fluidics control system has been manufactured using LIGA (Lithographie Galvanoformung und Abformung), Etching, Lithography and Laser etc. However, it is difficult that above-mentioned methods are applied to fabrication of precision mold master efficiently because of long processing time and rising cost of equipments. Therefore, in this study, micro EDM and micro WEDG system were developed to analyze machining characteristics with tool wear, surface roughness and process time. Then, optimal machining conditions could be obtained from the results of analysis. As the results, mold master of staggered herringbone mixer which has a high mixing efficiency, one of passive mixer of Lab-on-a-chip, could be fabricated from micro pattern(< 50um) using micro EDM successfully.

SoC를 이용한 소형 무선 센서 노드 설계 (Design of Miniaturized Wireless Sensor Node Using System-on-Chip)

  • 김현중;양현호
    • 한국산학기술학회:학술대회논문집
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    • 한국산학기술학회 2009년도 추계학술발표논문집
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    • pp.190-193
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    • 2009
  • 무선 센서 네트워크에서 가장 중요하고 기본적인 요소는 환경 정보를 수집하고 이를 사용자 응용시스템에 전송하는 무선 센서 노드이다. 무선 센서 노드는 센서로 환경 정보를 수집하고 이를 저장, 가공하여 처리된 데이터를 사용자에게 전송하는 무선 송수신 장치로 기술의 발전에 따라 소형화, 지능화되고 있다. 특히 마이크로컨트롤러, RF 모듈, 메모리 등을 하나의 칩 내부에 모두 통합하는 SoC(System-on-Chip)기술은 센서 노드의 소형화와 제조 단가를 낮추는데 중요한 역할을 한다. 본고에서는 상용 SoC를 사용하여 무선 센서 네트워크를 위한 소형 무선 센서 노드를 설계하였으며 이를 이용한 여러 활용 방안 및 추가적인 고려사항에 대하여 논하였다.

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비드를 이용한 면역분석용 마이크로필터 칩의 제작 (Microfilter Chip Fabrication for Bead-Based Immunoassay)

  • 이승우;안유민;채영규
    • 대한기계학회논문집A
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    • 제28권9호
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    • pp.1429-1434
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    • 2004
  • Immunoassay is one of the important analytical methods for clinical diagnoses and biochemical studies, but needs a long time, troublesome procedures and expensive reagents. In this study, therefore, we propose the micro filter chip with microbeads for immunoassay, which has pillar structures. The advantage of the proposed micro filter chip is to use simple fabrication process and cheap materials. The mold was made by the photolithography technique with Si wafer and negative photoresist SU-8. The replica was made of PDMS, bonded on the pyrex glass. The micro filter chip consists of inlet channel, filter chamber and outlet channel. HBV (Hepatitius B virus) monoclonal antibody (Ag1) labeled with biotin were immobilized onto streptavidin coated beads of 30∼50 $\mu$m size. Fluorescein isothiocyanate (FITC)-labeled HBV monoclonal antibody (Ag8) was used to detect HBsAg (Hebatitis B virus surface Antigen), and fluorescence intensity was monitored by epi-fluorescence microscope. In this study, the immune response of less than 30 min was obtained with with the use of 100 $m\ell$ of sample.

DNA Chip 데이터의 군집화 성능 향상을 위한 Particle Swarm Optimization 알고리즘의 적용기법 (Applying Particle Swarm Optimization for Enhanced Clustering of DNA Chip Data)

  • 이민수
    • 정보처리학회논문지D
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    • 제17D권3호
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    • pp.175-184
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    • 2010
  • 최근 DNA 칩의 등장으로 유전자 관련 실험과 연구가 매우 용이해졌으며 이를 활용한 다양한 실험 결과로 대량의 데이터가 제공되고 있다. DNA칩에 의해 제공된 데이터는 2차원 행렬로 표현되며 하나의 축은 유전자를 나타내고 다른 하나의 축은 샘플정보를 나타낸다. 이러한 데이터에 대하여 빠른 시간 안에 좋은 품질의 군집화를 수행함으로써 이후의 분석 단계인 분류화 작업의 정확도와 효율성을 높일 수 있다. 본 논문에서는 생태계 모방 알고리즘의 하나인 Particle Swarm Optimization 알고리즘을 사용하여 방대한 양의 DNA칩 데이터에 대한 효율적인 군집화 기법을 제안하였으며 실험을 통해서 PSO 기반의 군집화 알고리즘이 기존의 군집화 알고리즘들보다 수행속도 및 품질 면에서 우수한 성능을 가짐을 보였다.

Darveaux 모델에 의한 플립칩 패키지 솔더 접합부의 열피로 해석 및 수명 평가 (The Thermal Fatigue Analysis and Life Evaluation of Solder Joint for Flip Chip Package using Darveaux Model)

  • 신영의;김연성;김종민;최명기
    • Journal of Welding and Joining
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    • 제22권6호
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    • pp.36-42
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    • 2004
  • Experimental and numerical approaches on the thermal fatigue for the solder joint of flip chip package are discussed. However, it is one of the most difficult problems to choose the proper fatigue model. It was found that viscoplstic FE model with Darveaux method was very desirable and useful to predict the thermal fatigue life of solder joint for flip chip package under $208{\~}423K$ thermal cycling condition such as steep slope of temperature(JEDEC standard condition C). Thermal fatigue life was 1075 cycles as a result of viscoplatic model. It was a good agreement compared to the experimental. And also, it was found from the experimental that probability of the thermal fatigue life was $60{\%}$ at 1500 cycles.

H.264 Encoder Hardware Chip설계 (A design of Encoder Hardware Chip For H.264)

  • 김종철;서기범
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2008년도 추계종합학술대회 B
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    • pp.100-103
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    • 2008
  • 본 논문에서는 AMBA 기반으로 사용될 수 있는 H.264용 Encoder Hardware 모듈(Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, Motion Estimation)을 Integration하여 설계하였다. 설계된 모듈은 한 매크로 블록당 최대 440 cycle내에 동작한다. 제안된 Encoder 구조를 검증하기 위하여 JM 9.4부터 reference C를 개발하였으며, reference C로부터 test vector를 추출하며 설계 된 회로를 검증하였다. 제안된 회로는 최대 166MHz clock에서 동작하며, 합성결과 Charterd 0.18um 공정에 램 포함 약 180만 gate 크기이다. MPW제작시 chip size $6{\times}6mm$의 크기와 208 pin의 Pakage 형태로 제작하였다.

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