• The Journal of Korean Society for Radiation Therapy
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• v.25 no.1
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• pp.49-55
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• 2013

Purpose: Respiratory Gated Radiation Therapy (RGRT) has been carried out using RPM (Real-time Position Management) Respiratory Gating System (version 1.7.5, varian, USA) in Asan Medical Center. This study was to analyze and evaluate the accuracy of Respiratory Gated Radiation Therapy (RGRT) according to variation of respiration. Materials and Methods: Making variation of respiration using Motion Phantom:QUASAR Programmable Respiratory Motion Phantom (Moudus Medical Device Inc. CANADA) able to adjust respiration pattern randomly was varying period, amplitude and baseline by analyze 50 patient's respiration of lung and liver cancer. One of the variations of respiration is baseline shift gradually downward per 0.01 cm, 0.03 cm, 0.05 cm. The other variation of respiration is baseline shift accidently downward per 0.2 cm, 0.4 cm, 0.6 cm, 0.8 cm. Experiments were performed in the same way that is used RPM Respiratory Gating System (phase gating, usually 30~70% gating) in Asan Medical Center. Results: It was all exposed radiation under one of the conditions of baseline shift gradually downward per 0.01 cm, 0.03 cm, 0.05 cm. Under the other condition of baseline shift accidently downward per 0.2 cm, 0.4 cm, 0.6 cm, 0.8 cm equally radiation was exposed. Conclusion: The variations of baseline shifts didn't accurately reflect on phase gating in RPM Respiratory Gating System. This inexactitude makes serious uncertainty in Respiratory Gated Radiation Therapy. So, Must be stabilized breathing of patient before conducting Respiratory Gated Radiation Therapy. also must be monitored breathing of patient in the middle of treatment. If you observe considerable changes of breathing when conducting Respiratory Gated Radiation Therapy. Stopping treatment immediately and then must be need to recheck treatment site using fluoroscopy. If patient's respiration rechecked using fluoroscopy restabilize, it is possible to restart Respiratory Gated Radiation Therapy.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Korean Journal of Remote Sensing
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• v.18 no.1
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• pp.53-59
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• 2002

The MSC is a payload on the KOMPSAT-2 satellite to perform the earth remote sensing. The instrument images the earth using a push-broom motion with a swath width of 15 km and a GSD(Ground Sample Distance) of 1 m over the entire FOV(Field Of View) at altitude 685 km. The instrument is designed to haute an on-orbit operation duty cycle of 20% over the mission lifetime of 3 years with the functions of programmable gain/offset and on-board image data compression/storage. The MSC instrument has one channel for panchromatic imaging and four channel for multi-spectral imaging covering the spectral range from 450nm to 900nm using TDI(Time Belayed Integration) CCD(Charge Coupled Device) FPA(Focal Plane Assembly). The MSC hardware consists of three subsystem, EOS(Electro Optic camera Subsystem), PMU(Payload Management Unit) and PDTS(Payload Data Transmission Subsystem) and each subsystems are currently under development and will be integrated and verified through functional and space environment tests. Final verified MSC will be delivered to spacecraft bus for AIT(Assembly, Integration and Test) and then COMSAT-2 satellite will be launched after verification process through IST(Integrated Satellite Test). In this paper, the introduction of MSC, the configuration of MSC electronics including electrical interlace and design of CEU(Camera Electronic Unit) in EOS are described. MSC Operation parameters induced from the operation concept are discussed and analyzed to find the influence of system for on-orbit operation in future.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}