• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.199-202
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• 1999

In this paper, a possibility of building various types of RF passive components using the silicon micromachining technique has been examined with special emphasis on the wireless and mobile communication applications. Silicon micromachining technique is compatible with conventional silicon IC process and could provide a possibility of integrating base-band signal processing units and RF passive and active circuit components all in one silicon wafer rendering implementation of system-on-chip paradigm for future mobile and wireless communication systems.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.157-160
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• 2001

We studied about the lighting control system on pc using PLM(Power Line Modem). The PLM is composed of FSK IC-chip and the circuit for the power line communication. We developed the control program using visual c++ language on PC for dimming the lamps. In this paper dimming controller was made with PIC161F874 and its communication speed was 1200 boad rates.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1427-1434
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• 2013

In this paper, triple band mobile chip antenna for DCS(1.71~1.88GHz) / PCS(1.75~1.87GHz) / UPCS(1.85~1.99GHz) on PCB Layout is designed. To analyze the characteristics of the designed antenna, we designed and measured Single, Dual, Triple Band antenna. The designed antenna was fabricated and measured using vector network analyzer in LTK(Laird Technologies Korea). Triple and wide band characteristic could be realized the measured bandwidth(V.S.W.R<2.0) of designed antenna operated in the band of 1.71GHz~1.99GHz. This antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is a defect of chip antenna is improved. And its experimental results were a good agreement with simulation performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.86-93
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• 1997

A Design & Simulation Tools of Surface Acoustic Wave(SAW) Filters for Mobile Communication Systems, which is based on Optimization of Impulse Samples with Object Function of Amplitude, Ripple and Group Delay Characteristics, is developed and is also evaluated by designning and simulating the SAW IF Filter for PCS. In Optimization Process, fast calculation algorithm of Object Function is proposed. With this Design Tools, Transversal SAW IF Filters can be easily designed under limited conditions of small chip size and package size. It may be also applicable to wide Band Pass Filters in future Communication Systems such as FPLMTS.

• Korean Journal of Optics and Photonics
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• v.23 no.6
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• pp.269-273
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• 2012

It is important to control the beam pattern of an LED by the design of a reflector. The optimum conditions of the structure parameters for the 2 segment LED reflector are analyzed and compared as they vary depending on the various intensity distributions of light output on the LED chip surface. It is also interesting that combining various types of reflectors is possible to give several efficient beam patterns, such as the maximum intensity profile or relatively wide controllability of beam angle.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1899-1907
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• 2013

This paper presents an efficient defect detection and classification system based on reference image for COF (Chip-on-Film) which encounters fatal defects after ultra fine pattern fabrication. These defects include typical ones such as open, mouse bite (near open), hard short and soft short. In order to detect these defects, conventionally it needs visual examination or electric circuits. However, these methods requires huge amount of time and money. In this paper, based on reference image, the proposed system detects fatal defect and efficiently classifies it to one of 4 types. The proposed system includes the preprocessing of the test image, the extraction of ROI, the analysis of local binary pattern and classification. Through simulations with lots of sample images, it is shown that the proposed system is very efficient in reducing huge amount of time and money for detecting the defects of ultra fine pattern COF.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.1
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• pp.89-96
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• 2000

In this paper, we propose a vision algorithm for the inspection of very small RF-chip inductor which is used in mobile-communication terminal. The proposed method divides coil part from the inductor body by local adaptive thresholding and integral projection method. After dividing work, the coil components are extracted by thinning and labelling techniques. The test items are the number of turns, the intervals in coil, and the measure of uniformity between the extracted lines. If the values of these are more than the specific value a tested product is decided bad one. In the simulation, the proposed method has a good performance.

• ETRI Journal
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• v.46 no.2
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• pp.323-332
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• 2024

Receiver and transmitter monolithic microwave integrated circuit (MMIC) multifunction chips (MFCs) for active phased-array antennas for Ka-band satellite communication (SATCOM) terminals have been designed and fabricated using a 0.15-㎛ GaAs pseudomorphic high-electron mobility transistor (pHEMT) process. The MFCs consist of four-channel radio frequency (RF) paths and a 4:1 combiner. Each channel provides several functions such as signal amplification, 6-bit phase shifting, and 5-bit attenuation with a 44-bit serial-to-parallel converter (SPC). RF pads are implemented on the bottom side of the chip to remove the parasitic inductance induced by wire bonding. The area of the fabricated chips is 5.2 mm × 4.2 mm. The receiver chip exhibits a gain of 18 dB and a noise figure of 2.0 dB over a frequency range from 17 GHz to 21 GHz with a low direct current (DC) power of 0.36 W. The transmitter chip provides a gain of 20 dB and a 1-dB gain compression point (P1dB) of 18.4 dBm over a frequency range from 28 GHz to 31 GHz with a low DC power of 0.85 W. The P1dB can be increased to 20.6 dBm at a higher bias of +4.5 V.