• 한국CDE학회논문집
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• 제8권4호
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• pp.212-221
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• 2003

In order to reduce the lead-time and cost, the technology of rapid prototyping (RP) has been widely used. A new rapid prototyping process, transfer-type variable lamination manufacturing process by using expandable polystyrene foam (VLM-ST), has been developed to reduce building time, apparatus cost and additional post-processing. At the same time, VLM Slicer, the CAD/CAM software for VLM-ST has been developed. In this study, algorithms for accuracy improvement of VLM-ST, which include offset and overrun of a cutting path and generation of a reference shape are developed. Offset algorithm improves cutting accuracy, overrun algorithm enables the VLM-ST process to make a shape of sharp edge and reference shape generation algorithm adds additional shape which makes off-line lamination easier. In addition, proposed algorithms are applied to practical CAD models for verification.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1948-1951
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• 2002

In this paper, we propose a chip timing recovery algorithm that is robust to frequency offset and time variant fading environments for DS/CDMA. The proposed structure is a modified non-coherent Delay Locked Loop (DLL) that employs a decimator. Analytical expression for the proposed non-coherent DLL S-curve and steady-state timing jitter is derived and confirmed by computer simulation. The results show that the proposed structure can reduce a steady-state timing jitter of the regenerated spreading code replica to frequency offset and time-variant fading in mobile radio channel, especially in very low SNR.

• Journal of Communications and Networks
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• 제9권3호
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• pp.312-318
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• 2007

In this paper, we propose the optimal offset-time decision (OOD) algorithm which can effectively reduce the pre-transmission delay compared to the perfect isolation model, and can also be extended to general n priority classes while the target loss probability of each class is guaranteed for the variable offered load. In order to drive the OOD algorithm, we first analyze the loss probability of each priority class through class aggregation and iteration method; the analytic results obtained through the proposed algorithm are then validated with results garnered from extensive simulation tests.

• 제어로봇시스템학회논문지
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• 제19권2호
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• pp.125-130
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• 2013

Compared to OWR (One-Way Ranging) method that requires precise network time synchronization, TWR (Two-Way Ranging) method has advantages in building an indoor WPAN (Wireless Personal Area Network) location system with lower cost. However, clock offsets of nodes in WPAN system should be eliminated or compensated to improve location accuracy of the TWR method. Because conventional clock offset elimination methods requires multiple TWR transactions to reduce clock offset, they produce network traffic burden instead. This paper presents a clock offset estimation method that can reduce clock offset error with a single TWR transaction. After relative clock offsets of sensor nodes are estimated, clock offsets of mobile tags are estimated using a single TWR communication. Simulation results show that location accuracy of the proposed method is almost similar to the conventional clock offset elimination method, while its network traffic is about a half of the conventional method.

• 한국통신학회논문지
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• 제23권5호
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• pp.1270-1281
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• 1998

주파수 옵셋은 OFDM 신호의 부채널간 간섭을 유발하며, 수신 신호의 진폭과 위상을 왜곡시켜 전체적인 시스템 성능에 심각한 영향을 미친다. 본 논문에서는 이러한 주파수 옵셋을 추정하기 위해서 특정 부채널을 동기채널로 할당하고 파일럿 심벌을 전송하여 주파수 옵셋을 추정하는 개선된 최우 추정 방식을 제안하며, 제안된 주파수 옵셋 추정기의 오차 성능을 해석적으로 유도한다. 제안된 방식에서는 coherent 위상 변화에 의해 발생된 주파수 옵셋 부분을 증가 시키고 랜덤 위상 오차에 의해 발생된 주파수 옵셋 부분을 감소시킴으로써 주파수 옵셋 추정기의 성능을 향상시킨다. 모의 실험을 통하여 본 논문에서, 해석적으로 유도된 제안된 주파수 옵셋 추정기의 오차 분산의 upper bound가 올바르며, 제안된 추정기가 기존의 방식에 비해 오차 분산, 추적 범위, 시변 채널 영향의 면에서 우수하다는 것을 확인한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 추계종합학술대회
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• pp.162-165
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• 2000

본 논문에서는 AWGN 환경하에서 Direct-conversion 수신기 시스템에서 발생하는 DC offset을 제거하여 성능을 개선할 수 있는 방안으로 UC offset이 발생한 신호를 loop를 통해 누적, 평균화 하여 시변 DC offset 발생에 대처할 수 있는 방안을 모색하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.319-320
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• 2008

In this paper, we propose a new frequency offset estimation algorithm for DBO-CSS which is a standard for wireless personal area network (WPAN). In DBO-CSS, there can be several integer multiples of $2{\pi}$ in the phase rotation caused by the frequency offset because of the long time difference between the samples of differential relation and the high permissible frequency offset of the crystal oscillators between the transmitter and the receiver. In this paper, we propose an estimation algorithm by using the relationships of each sub-chirp signals to find the integer part without phase ambiguity.

• 대한기계학회논문집A
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• 제30권6호
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• pp.678-683
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• 2006

In this paper, the 5-axis tool path that has been generated from the original surface is, newly generated from the offset polyhedral mesh. In this approach, the interference check between two solid models can be simplified to that of offset polyhedral mesh and axis line. The tool path computation and interference check based on the offset mesh is simpler and faster than that based on the original surface. But 5-axis tool path generation using this approach is able to apply only for ball endmill and still takes longer time than 3-axis tool path generation.

• Journal of Advanced Marine Engineering and Technology
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• 제22권1호
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• pp.52-66
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• 1998

An experimental study on the flow characteristics was performed for a two-dimensional turbulent wall attaching offset jet at different oblique angles to a surface. The flow characteristics were investigated by using a split film probe with the modified Stock's calibration method. The jet mean velocity, turbulent intensity, wall static pressure coefficient profiles, and time-averaged reattachment point were measured at the Reynolds number Re (based on the nozzle width, D) ranging from 17700 to 53200, the offset ratio H/D from 2.5 to 10, and the inclined angle .alpha. from 0.deg. C to 40.deg. C. The Correlations between the maximum pressure position, minimum pressure position, and reattachment point and offset ratios, and inclined angles are presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.963-966
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• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.