• Title/Summary/Keyword: Non-volatile counter

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Design Space Exploration of EEPROM-SRAM Hybrid Non-volatile Counter Considering Energy Consumption and Memory Endurance (에너지 소비 및 메모리 내구성을 고려한 EEPROM-SRAM 하이브리드 비휘발성 카운터의 설계 공간 탐색)

  • Shin, Donghwa
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.4
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    • pp.201-208
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    • 2016
  • Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

Performance Analysis of Adaptive Partition Cache Replacement using Various Monitoring Ratios for Non-volatile Memory Systems

  • Hwang, Sang-Ho;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.23 no.4
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    • pp.1-8
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    • 2018
  • In this paper, we propose an adaptive partition cache replacement policy and evaluate the performance of our scheme using various monitoring ratios to help lifetime extension of non-volatile main memory systems without performance degradation. The proposal combines conventional LRU (Least Recently Used) replacement policy and Early Eviction Zone (E2Z), which considers a dirty bit as well as LRU bits to select a candidate block. In particular, this paper shows the performance of non-volatile memory using various monitoring ratios and determines optimized monitoring ratio and partition size of E2Z for reducing the number of writebacks using cache hit counter logic and hit predictor. In the experiment evaluation, we showed that 1:128 combination provided the best results of writebacks and runtime, in terms of performance and complexity trade-off relation, and our proposal yielded up to 42% reduction of writebacks, compared with others.

Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory

  • Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.11-20
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    • 2008
  • The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

3-bit Up/Down Counter based on Magnetic-Tunnel-Junction Elements (Magnetic-Tunnel-Junction 소자를 이용한 3비트 업/다운 카운터)

  • Lee, Seung-Yeon;Kim, Ji-Hyun;Lee, Gam-Young;Yang, Hee-Jung;Lee, Seung-Jun;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.1
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    • pp.1-7
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    • 2007
  • An MTJ element not only computes Boolean function but also stores the output result in itself. We can make the most use of magneto-logic's merits by employing the magneto-logic in substitution for the sequential logic as well as the combinational logic. This unique feature opens a new horizon for potential application of MTJ as a universal logic element. Magneto-logic circuits using MTJ elements are more integrative and non-volatile. This paper presents novel 3-bit magneto-logic up/down counters and presents simulation results based on the HSPICE macro-model of MTJ that we have developed.