• 대한임베디드공학회논문지
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• 제11권4호
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• pp.201-208
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• 2016

Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

• 한국컴퓨터정보학회논문지
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• 제23권4호
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• pp.1-8
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• 2018

In this paper, we propose an adaptive partition cache replacement policy and evaluate the performance of our scheme using various monitoring ratios to help lifetime extension of non-volatile main memory systems without performance degradation. The proposal combines conventional LRU (Least Recently Used) replacement policy and Early Eviction Zone (E2Z), which considers a dirty bit as well as LRU bits to select a candidate block. In particular, this paper shows the performance of non-volatile memory using various monitoring ratios and determines optimized monitoring ratio and partition size of E2Z for reducing the number of writebacks using cache hit counter logic and hit predictor. In the experiment evaluation, we showed that 1:128 combination provided the best results of writebacks and runtime, in terms of performance and complexity trade-off relation, and our proposal yielded up to 42% reduction of writebacks, compared with others.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• 대한전자공학회논문지SD
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• 제44권1호
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• pp.1-7
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• 2007

MTJ (Magnetic Tunneling Junction) 소자는 불 (Boolean) 연산을 수행할 수 있을 뿐만 아니라, 자신의 출력 정보를 저장하는 비휘발성 소자이다. 기존의 트랜지스터로 구성된 논리 연산자를 MTJ 소자로 대체함으로써, 조합논리 회로와 순차논리 회로로 구성된 디지털 논리 회로를 자기논리 (magneto-logic) 회로로 대체 가능하다. 또한 자기논리 회로는 비휘발성 논리 소자를 사용함으로써, 회로 면적 면에서 우수하고 전원이 꺼져도 정보를 유지할 수 있는 장점을 가지고 있다. 본 논문에서는 이러한 자기논리 회로의 예로 3비트 업/다운 카운터를 설계하였고 그 동작을 이전 논문에서 제안된 바 있는 macro-model을 보완 적용하여 검증하였다.