• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.139-144
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• 2019

For recent decades, Non-volatile Memory (NVM) technologies have been drawing a high attention both in industry and academia due to its high density and short latency comparable to that of DRAM. However, NVM devices has write endurance problem and thus the current data structures that have been built around DRAM-specific features including unlimited program cycles is inadequate for NVM, reducing the device lifetime significantly. In this paper, we revisit a red-black tree extensively adopted for data indexing across a wide range of applications, and make it to better fit for NVM. Specifically, we observe that the conventional red-black tree wears out the specific location of memory because of its rebalancing operation to ensure fast access time over a whole dataset. However, this rebalancing operation frequently updates the long-lived nodes, which leads to the skewed wear out across the NVM cells. To resolve this problem, we present a new swapping wear-leveling red-black tree that periodically moves data in the worn-out node into the young node. The performance study with real-world traces demonstrates the proposed red-black tree reduces the standard deviation of the write count across nodes by up to 12.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1123-1127
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• 2009

This paper expands the scope of application of the thin film transistor (TFT) in which it is used as the switching element by making the amorphous silicon TFT with the non-volatile memory device,. It is the thing about the amorphous silicon non-volatile memory device which is suitable to an enlargement and in which this uses the additionally cheap substrate according to the amorphous silicon use. As to, the amorphous silicon TFT non-volatile memory device is comprised of the glass substrates and the gate, which evaporates on the glass substrates and in which it patterns the first insulation layer, in which it charges the gate the floating gate which evaporates on the first insulation layer and in which it patterns and the second insulation layer in which it charges the floating gate, and the active layer, in which it evaporates the amorphous silicon on the second insulation layer the source / drain layer which evaporates the n+ amorphous silicon on the active layer and in which it patterns and the source / drain layer electrode in which it evaporates on the source / drain layer.

• KIISE Transactions on Computing Practices
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• v.22 no.10
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• pp.497-503
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• 2016

Emerging next-generation storage technologies such as non-volatile memory will help eliminate almost all of the storage latency that has plagued previous storage devices. In conventional storage systems, the latency of slow storage devices dominates access latency; hence, software efficiency is not critical. With low-latency storage, software costs can quickly dominate memory latency. Hence, researchers have proposed the memory mapped file I/O to avoid the software overhead. Mapping a file into the user memory space enables users to access the file directly. Therefore, it is possible to avoid the complicated I/O stack. This minimizes the number of user/kernel mode switchings. In addition, there is no data copy between kernel and user areas. Despite of the benefits in the memory mapped file I/O, its overhead still needs to be addressed, as the existing mechanism for the memory mapped file I/O is designed for slow block devices. In this paper, we identify the overheads of the memory mapped file I/O via experiments.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.2-211.2
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• 2014

Epitaxial complex oxide thin film heterostructures have attracted a great attention for their multifunctional properties, such as ferroelectricity, and ferromagnetism. Two dimensional electron gas (2DEG) confined at the interface between two insulating perovskite oxides such as LaAlO3/SrTiO3 interface, provides opportunities to expand various electronic and memory devices in nano-scale. Recently, it was reported that the conductivity of 2DEG could be controlled by external electric field. However, the switched conductivity of 2DEG was not stable with time, resulting in relaxation due to the reaction between charged surface on LaAlO3 layer and atmospheric conditions. In this report, we demonstrated a way to control the conductivity of 2DEG in non-volatile way integrating ferroelectric materials into LAO/STO heterostructure. We fabricated epitaxial Pb(Zr0.2Ti0.8)O3 films on LAO/STO heterostructure by pulsed laser deposition. The conductivity of 2DEG was reproducibly controlled with 3-order magnitude by switching the spontaneous polarization of PZT layer. The controlled conductivity was stable with time without relaxation over 60 hours. This is also consistent with robust polarization state of PZT layer confirmed by piezoresponse force microscopy. This work demonstrates a model system to combine ferroelectric material and 2DEG, which guides a way to realize novel multifunctional electronic devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2006.11a
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• pp.14.1-14.1
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• 2006

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.274-282
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• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• Journal of Advanced Marine Engineering and Technology
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• v.29 no.6
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• pp.707-712
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• 2005

PRAM (Phase change random access memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change materials have been researched in the field of optical data storage media. Among the phase change materials. $Ge_2Sb_2Te_5$ is very well known for its high optical contrast in the state of amorphous and crystalline. However the characteristics required in solid state memory are quite different from optical ones. In this study. the structural Properties of GeSbTe thin films with composition were investigated for PRAM. The 100-nm thick $Ge_2Sb_2Te_5$ and $Sb_2Te_3$ films were deposited on $SiO_2/Si$ substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films. x-ray diffraction (XRD). atomic force microscopy (AFM), differential scanning calorimetry (DSC) and 4-point measurement analysis were performed. XRD and DSC analysis result of GST thin films indicated that the crystallization of $Se_2Sb_2Te_5$ films start at about $180^{\circ}C$ and $Sb_2Te_3$ films Start at about $125^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.