• Title/Summary/Keyword: Node-wise Density

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Reduced Complexity-and-Latency Variable-to-Check Residual Belief Propagation for LDPC Codes (LDPC 부호를 위한 복잡도와 대기시간을 낮춘 VCRBP 알고리즘)

  • Kim, Jung-Hyun;Song, Hong-Yeop
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.6C
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    • pp.571-577
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    • 2009
  • This paper proposes some new improved versions of node-wise VCRBP algorithm for low-density parity-check (LDPC) codes, called forced-convergence node-wise VCRBP algorithm and sign based node-wise VCRBP, both of which significantly reduce the decoding complexity and latency, with only negligible deterioration in error correcting performance.

Exploration of static and free vibration resistance topologically optimal beam structure shapes using density design variables. (재료밀도 설계변수를 이용한 정적 및 자유진동 저항 위상최적 보의 형상 탐색에 관한 연구)

  • Lee, Dongkyu;Shin, Soo Mi
    • Journal of Korean Association for Spatial Structures
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    • v.24 no.1
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    • pp.57-64
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    • 2024
  • This study numerically compares optimum solutions generated by element- and node-wise topology optimization designs for free vibration structures, where element-and node-wise denote the use of element and nodal densities as design parameters, respectively. For static problems optimal solution comparisons of the two types for topology optimization designs have already been introduced by the author and many other researchers, and the static structural design is very common. In dynamic topology optimization problems the objective is in general related to maximum Eigenfrequency optimization subject to a given material limit since structures with a high fundamental frequency tend to be reasonable stiff for static loads. Numerical applications topologically maximizing the first natural Eigenfrequency verify the difference of solutions between element-and node-wise topology optimum designs.

Topology Optimization of Plane Structures under Free Vibration with Isogeometric Analysis (등기하해석법을 이용한 자유진동 평면구조물의 위상최적화)

  • Lee, Sang-Jin;Bae, Jungeun
    • Journal of the Architectural Institute of Korea Structure & Construction
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    • v.34 no.6
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    • pp.11-18
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    • 2018
  • Isogeometric concept is introduced to find out the optimum layout of plane structure under free vibration. Eigenvalue problem is formulated and numerically solved in order to obtain natural frequencies and mode shapes of plane structures. For the exact geometric expression of the structure, the Non-Uniform Rational B-spline Surface (NURBS) basis functions is employed and it is also used to define the material density functions. A node-wise design variables is adopted to deal with the updating of material density in topology optimization (TO). The definition of modal strain energy is employed to achieve the maximization of fundamental frequency through its minimization. The verification of the proposed TO technique is performed by a series of benchmark test for plane structures.

The effect of 1/f Noise Caused by Random Telegraph Signals on The Phase Noise and The Jitter of CMOS Ring Oscillator (Random Telegraph Signal에 의한 1/f 잡음이 CMOS Ring Oscillator의 Phase Noise와 Jitter에 미치는 영향)

  • 박세훈;박세현;이정환;노석호
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2004.05b
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    • pp.682-684
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    • 2004
  • The effect of 1/f noise by the random telegraph signal(RTS) on the phase noise and the jitter of CMOS ring Oscillator is investigated. 10 parallel piece-wise-linear current sources connected to each node model the RTS signals. The In, the power spectral density and the jitter of output of the ring oscillator are simulated as functions of the amplitude and time constant of RTS current source. It is confirmed that the increase of amplitude of RTS is directly related to the increase of the width of phase noise md the value of jitter. The shorter the time constant is, the wider width of FET peak and the larger value of cycle to cycle jitter are.

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Design of High Speed LDPC Encoder Based on DVB-S2 Standard (DVB-S2 기반 고속 LDPC 부호기 설계)

  • Park, Gun Yeol;Lee, Seong Ro;Jeon, Sung Min;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.2
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    • pp.196-201
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    • 2013
  • In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.