• Title/Summary/Keyword: Nickel silicide

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Direct Bonding of Si(100)/NiSi/Si(100) Wafer Pairs Using Nickel Silicides with Silicidation Temperature (열처리 온도에 따른 니켈실리사이드 실리콘 기판쌍의 직접접합)

  • Song, O-Seong;An, Yeong-Suk;Lee, Yeong-Min;Yang, Cheol-Ung
    • Korean Journal of Materials Research
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    • v.11 no.7
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    • pp.556-561
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    • 2001
  • We prepared a new a SOS(silicon-on-silicide) wafer pair which is consisted of Si(100)/1000$\AA$-NiSi Si (100) layers. SOS can be employed in MEMS(micro- electronic-mechanical system) application due to low resistance of the NiSi layer. A thermally evaporated $1000\AA$-thick Ni/Si wafer and a clean Si wafer were pre-mated in the class 100 clean room, then annealed at $300~900^{\circ}C$ for 15hrs to induce silicidation reaction. SOS wafer pairs were investigated by a IR camera to measure bonded area and probed by a SEM(scanning electron microscope) and TEM(transmission electron microscope) to observe cross-sectional view of Si/NiSi. IR camera observation showed that the annealed SOS wafer pairs have over 52% bonded area in all temperature region except silicidation phase transition temperature. By probing cross-sectional view with SEM of magnification of 30,000, we found that $1000\AA$-thick uniform NiSi layer was formed at the center area of bonded wafers without void defects. However we observed debonded area at the edge area of wafers. Through TEM observation, we found that $10-20\AA$ thick amourphous layer formed between Si surface and NiSix near the counter part of SOS. This layer may be an oxide layer and lead to degradation of bonding. At the edge area of wafers, that amorphous layer was formed even to thickness of $1500\AA$ during annealing. Therefore, to increase bonding area of Si NiSi ∥ Si wafer pairs, we may lessen the amorphous layers.

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Nickel Film Deposition Using Plasma Assisted ALD Equipment and Effect of Nickel Silicide Formation with Ti Capping Layer (Plasma Assisted ALD 장비를 이용한 니켈 박막 증착과 Ti 캡핑 레이어에 의한 니켈 실리사이드 형성 효과)

  • Yun, Sang-Won;Lee, Woo-Young;Yang, Chung-Mo;Ha, Jong-Bong;Na, Kyoung-Il;Cho, Hyun-Ick;Nam, Ki-Hong;Seo, Hwa-Il;Lee, Jung-Hee
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.3
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    • pp.19-23
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    • 2007
  • The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

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Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique

  • Kim, Hyun Woo;Kim, Jong Pil;Kim, Sang Wan;Sun, Min-Chul;Kim, Garam;Kim, Jang Hyun;Park, Euyhwan;Kim, Hyungjin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.572-578
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    • 2014
  • In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

Formation of Nickel Silicide from Atomic Layer Deposited Ni film with Ti Capping layer

  • Yun, Sang-Won;Lee, U-Yeong;Yang, Chung-Mo;Na, Gyeong-Il;Jo, Hyeon-Ik;Ha, Jong-Bong;Seo, Hwa-Il;Lee, Jeong-Hui
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2007.06a
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    • pp.193-198
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    • 2007
  • The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

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Dependence of contact resistance in SiC device by annealing conditions (어닐링 조건에 의한 SiC 소자에서 콘택저항의 변화)

  • Kim, Seong-Jeen
    • Journal of IKEEE
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    • v.25 no.3
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    • pp.467-472
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    • 2021
  • Stable operation of semiconductor devices is needed even at high temperatures. Among the structures of semiconductor devices, the area that can cause unstable electrical responses at high temperatures is the contact layer between the metal and the semiconductor. In this study, the effect of annealing conditions included in the process of forming a contact layer of nickel silicide(NiSix) on a p-type SiC layer on the specific contact resistance of the contact layer and the total resistance between the metal and the semiconductor was investigated. To this end, a series of electrodes for TLM (transfer length method) measurements were patterned on the 4 inch p-type SiC layer under conditions of changing annealing temperature of 1700 and 1800 ℃ and annealing time of 30 and 60 minutes. As a result, it was confirmed that the annealing conditions affect the resistance of the contact layer and the electrical stability of the device.

Interfacial Adhesion Energy of Ni-P Electroless-plating Contact for Buried Contact Silicon Solar Cell using 4-point Bending Test System (4점굽힘시험법을 이용한 함몰전극형 Si 태양전지의 무전해 Ni-P 전극 계면 접착력 평가)

  • Kim, Jeong-Kyu;Lee, Eun-Kyung;Kim, Mi-Sung;Lim, Jae-Hong;Lee, Kyu-Hwan;Park, Young-Bae
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.1
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    • pp.55-60
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    • 2012
  • In order to develop electroless-plated Nickel Phosphate (Ni-P) as a contact material for high efficient low-cost silicon solar cells, we evaluated the effect of ambient thermal annealing on the degradation behavior of interfacial adhesion energy between electroless-plated Ni-P and silicon solar cell wafers by applying 4-point bending test method. Measured interfacial adhesion energies decreased from 14.83 to 10.83 J/$m^2$ after annealing at 300 and $600^{\circ}C$, respectively. The X-ray photoelectron spectroscopy analysis suggested that the bonding interface was degraded by environmental residual oxygen, in which the oxidation inhibit the stable formation of Ni silicide phase between electroless-plated Ni-P and silicon interface.