• 한국초전도ㆍ저온공학회논문지
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• 제8권3호
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• pp.32-36
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• 2006

Simplification of the buffer architecture in the fabrication of coated conductors is required because the deposition of multi-layers leads to a longer production time and a higher cost of coated conductors. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique. l00nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $0.4{\mu}m$-thick SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-W substrate. Critical current of $55.4 A/cm^2$ was obtained for the SmBCO coated conductors.

• 한국전기전자재료학회논문지
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• 제20권6호
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• pp.546-549
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• 2007

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost. Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique. 100 nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $1\;{\mu}m-thick$ SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-5%W substrate. Critical current of 90 A/cm was obtained for the SmBCO coated conductors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.180-181
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• 2006

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique 100nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $0.4{\mu}m$-thick SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-W substrate. Critical current of 118A/$cm^2$ was obtained for the SmBCO coated conductors.

• 한국초전도ㆍ저온공학회논문지
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• 제8권3호
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• pp.9-12
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• 2006

Batch type co-evaporation EDDC (Evaporation using Drum in Dual Chambers) system was recently manufactured to fabricate 100m - long SmBCO superconducting coated conductor. As a preliminary study before the fabrication of long tape. short CC samples have been fabricated using the EDDC system and their crystal texture and $I_c$ properties were investigated. $1.2 {\mu}m$-thick SmBCO layers were deposited on $CeO_2/YSZ/CeO_2$ buffered Ni-W tapes. $I_c$ of 128A/cm-w and corresponding $J_c$ of $1.1 MA/cm^2$ at 77K in self-field were obtained for SmBCO CC tape. In-field property of SmBCO CC was confirmed to be better than that of YBCO deposited by PLD.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1356-1361
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• 2004

High temperature superconducting coated conductor has a structure of ///. The buffer layer consists of multi-layer, this study reports the deposition method and optimal deposition conditions of YSZ(Yttria-stabilized zirconia) layer which plays a important part in preventing the elements of substrate from diffusing into the superconducting layer. YSZ layer was deposited by DC reactive sputtering technique using water vapor for oxidizing deposited elements on substrate. To investigate optimal thickness of YSZ film, four YSZ/CeO$_2$/Ni samples with different YSZ thickness(130 nm, 260 nm, 390 nm, and 650 nm) were prepared. The SEM image showed that the surface of YSZ layer was getting to be rougher as YSZ layer was getting thicker and the growth mode of YSZ layer was columnar grain growth. After CeO$_2$ layer was deposited with the same thickness of 18.3 nm on each four samples, YBCO layer was deposited by PLD method with the thickness of 300 nm. The critical currents of four samples were 0, 6 A, 7.5 A, and 5 A respectively. This shows that as YSZ layer is getting thicker, YSZ layer plays a good role as a diffusion barrier but the surface of YSZ layer is getting rougher.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.153-156
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• 2003

The multi-layer oxide buffer layer for the coated conductor was deposited on biaxially textured Ni substrates using pulsed laser deposition. Oxygen partial pressure, 4％$H_2$/Ar partial pressure, and deposition temperature were deposition variables investigated to find the optimum deposition conditions. $Y_2$O$_3$seed layer was deposited epitaxially on metal substrate. The full buffer architecture of $Y_2$O$_3$/YSZ/CeO$_2$was successfully prepared on metal substrate.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 추계학술대회 논문집
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• pp.158-158
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• 2009

The electrophoretic deposition(EPD) technique with a wide range of novel applications in the processing of advanced ceramic materials and coatings, has recently gained increasing interest both in academic and industrial sector not only because of the high versatility of its use with different materials and their combinations but also because of its cost-effectiveness requiring simple apparatus. Compared to other advanced shaping techniques, the EPD process is very versatile since it can be modified easily for a specific application. For example, deposition can be made on flat, cylinderical or any other shaped substrate with only minor charge in electrode design and positioning[1]. The synthesis of the nano-sized Ce0.2Sm0.8O1.9(SDC)particles prepared by aurea based low temperature hydrothermal process was investigated in this study[2].When we made the SDC nanoparticles, changed the time of synthesis of the SDC. The SDC nanoparticles were characterized with field-emission scanning electron microscope(FESEM), energy dispersive X-ray analysis(EDX), and X-ray diffraction(XRD). And also we researched the results of our investigation on electrophoretic deposition(EPD) of the SDC particles from its suspension in acetone solution onto a non-conducting NiO-SDC substrate. In principle, it is possible to carry out electrophoretic deposition on non-conducting substrates. In this case, the EPD of SDC particles on a NiO-SDC substrate was made possible through the use of a adequately porous substrate. The continuous pores in the substrates, when saturated with the solvent, helped in establishing a "conductive path" between the electrode and the particles in suspension[3-4]. Deposition rate was found to increase its increasing deposition time and voltage. After annealing the samples $1400^{\circ}C$, we observed that deposited substrate.

• Korean Chemical Engineering Research
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• 제49권6호
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• pp.781-785
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• 2011

본 연구에서는 나노 크기의 세리아를 사마리움으로 일부 도핑(samaria-doped ceria(SDC))한 분말을 urea를 첨가제로 사용하여 수열합성법으로 합성하였으며 그 특성들을 XRD, FESEM, TEM 등을 통해 관찰하였다. 합성 시간 및 합성온도가 증가함에 따라 분말의 결정성 및 입도가 증가함을 확인하였다. 또한 이온전도도의 측정을 통해 합성된 SDC 파우더가 중 저온(600~$800^{\circ}C$) 부근에서 0.1 S/cm의 이온전도도를 보여 중 저온형 고체산화물 연료전지(IT-SOFC)의 고체 전해질에 적합함을 확인할 수 있었다. 합성된 SDC 분말은 중·저온 고체산화물 연료전지의 음극지지형 전해질로 사용하기 위해 전기영동 증착 방법을 이용하여 다공성 NiO-SDC 기판 위에 SDC 박막 증착을 시도하였다. 증착 용액은 acetone을 용매로 사용하고, 20V의 인가전압으로 10초간 증착한 결과 얇고 치밀하며 기공이 없는 SDC 박막이 형성되었음을 FESEM 분석을 통해 확인할 수 있었다.

• 한국전기전자재료학회논문지
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• 제26권2호
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• pp.98-103
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• 2013

The alumina substrates that Ni electrode was printed on and the multi-layered PTCR thermistors of which composition is $(Ba_{0.998}Ce_{0.002})TiO_3+0.001MnCO_3+0.05BN$ were fabricated by a thick film process, and the effect of re-oxidation temperature on their resistivities and resistance jumps were investigated, respectively. Ni electroded alumina substrate and the multi-layered PTC thermistor were sintered at $1150^{\circ}C$ for 2 h under $PO_2=10^{-6}$ Pa and then re-oxidized at $600{\sim}850^{\circ}C$ for 20 min. With increasing the re-oxidation temperature, the room temperature resistivity increased and the resistance jump ($LogR_{290}/R_{25}$) decreased, which seems to be related to the oxidation of Ni electrode. The small sized chip PTC thermistor such as 2012 and 3216 exhibits a nonlinear and rectifying behavior in I-V curve but the large sized chip PTC thermistor such as 4532 and 6532 shows a linear and ohmic behavior. Also, the small sized chip PTC thermistor such as 2012 and 3216 is more dependent on the re-oxidation temperature and easy to be oxidized in comparison with the large sized chip PTC thermistor such as 4532 and 6532. So, the re-oxidation conditions of chip PTC thermistor may be determined by considering the chip size.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.339-339
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• 2002

In the RABiTS approach to coated conductor development, successful (both economic and technological) depends on the refinement and optimization of each of three important components: the metal tape substrate, the buffer layer(s), and the HTS layer. Here we will report on the ORNL approach and progress in each of these areas. - Most applications will require metal tapes with low magnetic hysteresis, mechanical strength, and excellent crystalline texture. Some of these requirements are competing. We report on progress in obtaining a good combination of these characteristics on metal alloys of Ni-Cr and Ni-W. - The deposition of appropriate buffer layers is a crucial step. Recently, base research has shown that the presence of a stable sulfur superstructure present on the metal surface is needed for the nucleation and epitaxial growth of vapor-deposited seed buffer layers such as YSZ, CeO$_2$ and SrTiO$_3$. We report on the details and control of this superstructure for nickel tapes, as well as recent results for Cu and Ni-13%Cr. - Processes for deposition of the HTS coating must economically provide large values of the figure-of-merit for conductors, current x length. At ORNL, we have devoted efforts to a precursor/post-annealing approach to YBCO coatings, for which the deposition and reaction steps are separate. We describe motivation for and progress toward developing this approach. - Finally, we address some issues for the implementation of coated conductors in real applications, including the need for texture control and electrical stabilization of the HTS coating.