• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2372-2382
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• 1998

In this paper, we propose a new edge based finite state vector quantization method having better performance than conventional side-match finite state vector quantization. In our proposed scheme, each dCT transformed block is classified to 17 classes according to edge types. Each class has a different codebook based on its characteristis. Encoder classified each block to motion block or stationary block and constructed a merging map by using edge and motion information, and sent to decoder. We controled amoutn of bing bits transmitted with selecting modes accoridng to bandwidth of transmitting channel. Compared with conventional algorithms, H.263 and H.261 at low bit rate, our proposed algorithm shows better picture quality and good performance.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.28-37
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• 1996

Syntax notation one (ASN.1) defined by ITU-T and ISO, is a formal abstrct specification language which has been widely used in international standards specifiation to inteconnect distributed open systems. It si necessary to have well defined encoder/decoder modules which taranslate ASN.1 datum to BER octets stream to interconnect distributed open systems. In this paper, we designed and implemented a new ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which atutomatically translates and ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which automatically translates an ASN.1 specification into C-language BER encoders and decoders with simple and neat I/F for the defined ASN.1 data types, and enhanced BER (basic encoding rules)encoding/decoding libraries, called HY(hanyang)BER library, and useful utility functions. And this paper discusses HYASNC compiler, HY BER runtime library's design and implementation principles, and also evaluates the perfomrance of HY BER library and the interoperability with other ASN.1 compilers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.8
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• pp.4255-4269
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• 2019

This paper proposes an image generation method using a Multi Discriminator Generative Adversarial Net (MDGAN) as a next generation 2D game sprite creation technique. The proposed GAN is an Autoencoder-based model that receives three areas of information-color, shape, and animation, and combines them into new images. This model consists of two encoders that extract color and shape from each image, and a decoder that takes all the values of each encoder and generates an animated image. We also suggest an image processing technique during the learning process to remove the noise of the generated images. The resulting images show that 2D sprites in games can be generated by independently learning the three image attributes of shape, color, and animation. The proposed system can increase the productivity of massive 2D image modification work during the game development process. The experimental results demonstrate that our MDGAN can be used for 2D image sprite generation and modification work with little manual cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• The Journal of the Korea Contents Association
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• v.12 no.8
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• pp.20-28
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• 2012

DVC(Distributed Video Coding) technique is a new paradigm, which is based on the Slepian-Wolf and Wyner-Ziv theorems. DVC offers not only flexible partitioning of the complexity between the encoder and decoder, but also robustness to channel errors due to intrinsic joint source-channel coding. Many conventional research works have been focused on the light video encoder and its rate-distortion performance improvement. However, in this paper, we propose a new DVC codec which is effectively applicable for error-prone environment. The proposed method adopts a quantiser without dead-zone and symmetric Gray code around zero value. Through computer simulations, the proposed method is evaluated by the bit errors position as well as the number of burst bit errors. Additionally, it is shown that the maximum and minimum transmission rate for the given application can be linearly determined by the number of bit errors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1182-1191
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• The Journal of the Acoustical Society of Korea
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• v.16 no.4
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• pp.64-70
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• 1997

This paper is aimed to propose a new wavelet audio signal coding scheme which reduces the complexity of well-known MPEG(Moving Picture Expert Group)-Audio. The filters of MPEG0audio apply subband technique on the 16-bits PCM audio to aquire bitstream of subband sample using dynamic bit allocation. If we use the wavelet coefficients instead of subband samples and 6 bands which is less than 32 bands of MPEG-audio, the complexity can be reduced. A new audio signal compression algorithm in this paper is based on wavelet transform and the proposed algorithm is compared with MPEG-audio. At the bitrate of 256kbps, the proposed algorithm maintains the CD(Compact-disc) quality. We were able to reduce the about 40% of complexity at encoder and about 70% at decoder.

• Journal of Broadcast Engineering
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• v.17 no.6
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• pp.1029-1039
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• 2012

In this papar, we propose a new motion estimation and coding technique using adaptive motion vector resolution. Currently, HEVC encodes a video using 1/4 motion vector resolution. If there are high texture regions in a picture, HEVC can't get a performance enough. So, we insert additional 1-bit flag meaning whether motion vector resolution is 1/4 or 1/8 in PU syntax. Therefore, decoder can recognize the transmitted motion vector resolution. Experimental results show that maximum coding efficiency gain of the proposed method is up to 5.3% in luminance and 7.9% in chrominance. Average computional time complexity is increased about 33% in encoder and up to 5% in decoder.

• Journal of Broadcast Engineering
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• v.12 no.6
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• pp.585-595
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• 2007

Distributed video coding is a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv's information theory Distributed video coding whose decoder exploits side information transfers its computational burden from encoder to decoder, so that encoding with light computational power can be realized. RD performance is superior than that of standard video coding without motion compensation process but still has a gap with that of coding with motion compensation process. This parer introduces basic theory of distributed video coding and its structure and then shows RD performances of DVCs whose coding style is different from each other and of a DVC as a spatial scalable video coder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1663-1670
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• 2014

Recently, lots of research works have been actively focused on the DVC (Distributed Video Coding) techniques which provide a theoretical basis for the implementation of light video encoder. However, most of these studies have showed poorer performances than the conventional standard video coding schemes such as MPEG-1/2, MPEG-4, H.264 etc. In order to overcome the performance limits of the conventional approaches, several channel-divided distributed video coding schemes have been designed in such a way that some information are obtained while generating side information at decoder side and then these are provided to the encoder side, resulting in channel-divided video coding scheme. In this paper, the interpolation scheme by weighted sum of multiple motion-compensated interpolation frames is introduced and a new channel-divided DVC scheme is designed to effectively describe noisy channels based on the motion vector and its matching characteristics. Through several simulations, it is shown that the proposed method performs better than the conventional methods at low bit-rate and keeps the reconstructed visual quality constantly.