• 제목/요약/키워드: Network Reduction

검색결과 1,410건 처리시간 0.026초

모선 간 유사지수에 근거한 새로운 계통축약 기법 (A Novel Network Reduction Method based on Similarity Index between Bus Pairs)

  • 전영환;이동수
    • 대한전기학회논문지:전력기술부문A
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    • 제55권4호
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    • pp.156-162
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    • 2006
  • Transmission zones can be defined based on LMPs. Each zone consists of nodes with similar LMPs, and zonal price is determined by average nodal prices in each zone.[1] Network reduction is still important for the analysis of zonal systems under electricity market environments, even though the computing capability of computer system can deal with entire power systems. The Similarity Index is a good performance measure for the network reduction.[2] It can be applied to the network reduction between zones categorized by the nodal prices. This paper deals with a novel network reduction method between zones based on the similarity Index. Line admittances of reduced network were determined by using the least square method. The proposed method was verified by IEEE 39 bus test system.

Weak Coupling Method를 이용한 계통 축약 (A Network Reduction using Weak Coupling Method)

  • 이한민;노규민;권세혁
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 C
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    • pp.1067-1069
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    • 1999
  • This paper presents a network reduction using weak coupling method. Weak coupling method of identifying coherent generator groups are proposed. The partitioning technique used in this paper is based on a property of sparse matrix factorization. When a matrix has been factorized, a system is divided into study area, boundary buses and external area. A reduction process for external system starts with the load bus elimination and coherent generator aggregation. An identification of coherent generator group, network partitioning and network reduction are presented.

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IT 중소벤처기업의 외부 정보 네트워크의 다양성과 생산성 향상 : 생산 기간 단축의 매개적 역할 (IT SME Ventures' External Information Network Diversity and Productivity Improvement : The Mediating Role of the Production Period Reduction)

  • 허용석
    • 산업경영시스템학회지
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    • 제40권1호
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    • pp.144-149
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    • 2017
  • This study empirically analyzes the effect of IT SME ventures' external information network diversity on their production period reduction and productivity improvement generated from technology development. This research constructs a mediating model based on the open innovation perspective and tests it with the 138 samples of South Korean IT SME ventures based on the ordinary least squares regression. This research is expected to make a good contribution by shedding a new light on the following three points about the critical role of IT SME ventures' external information network diversity in increasing their production period reduction and productivity improvement generated from technology development which has scarcely been illuminated in the extant studies in the field of the management of technology for SMEs. First, IT SME ventures' external information network diversity positively influences their production period reduction. Second, the external information network diversity positively influences IT SMEs' ventures' productivity improvement. Third, IT SME ventures' production period reduction partially mediates the influence of IT SME ventures' external network diversity on their productivity improvement. These three fresh points are expected to provide useful theoretical and practical implications. Related to the theoretical implication, this research provides a fresh implication that IT SME ventures' external information network diversity positively influences not only their production period reduction but also productivity improvement generated from technology development. Concerning the practical implication, this study suggests that the CEOs in IT SME ventures make strategic efforts to use more diverse external information sources in order to increase their production period reduction and productivity improvement generated from technology development.

송전망 축약을 위한 교육용 시뮬레이터 개발 (Development of Educational Simulator for Novel Network Reduction)

  • 김현홍;이우남;김욱;박종배;신중린
    • 전기학회논문지
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    • 제58권10호
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    • pp.1902-1910
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    • 2009
  • This paper presents a graphical windows-based program for the education and training for novel network reduction. The object of developed simulator is to provide users with a simple and useable tool for gaining an intuitive feel for power system analysis. The developed simulator consists of the main module (MMI,GUI), the location marginal price module (LMP), the clustering module and network reduction module. Each module has a separate graphical and interactive interfacing window. The developed simulator needs with the PSS/E input data format, generator cost function, location information. Line admittances of reduced network was determined by using the power flow method(Newton-Raphson). So line flow of reduced network is almost same to original power system. Results of reduced network are compared on the window in the tabular format. Therefore, the developed simulator can be utilized as a useful tool for effective education and training for power system analysis.

대형 회로망 그래프 마디축소 모델 (Node-reduction Model of Large-scale Network Grape)

  • 황재호
    • 대한전기학회논문지:시스템및제어부문D
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    • 제50권2호
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    • pp.93-99
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    • 2001
  • A new type geometric and mathematical network reduction model is introduced. Large-scale network is analyzed with analytic approach. The graph has many nodes, branches and loops. Circuit equation are obtained from these elements and connection rule. In this paper, the analytic relation between voltage source has a mutual different graphic property. Node-reduction procedure is achieved with this circuit property. Consequently voltage source value is included into the adjacent node-analyzing equation. A resultant model equations are reduced as much as voltage source number. Matrix rank is (n-1-k), where n, k is node and voltage source number. The reduction procedure is described and verified with geometric principle and circuit theory. Matrix type circuit equation can be composed with this technique. The last results shall be calculated by using computer.

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확률적 네트워크의 신뢰도 평가를 위한 분산 감소기법의 응용 (An Application of Variance Reduction Technique for Stochastic Network Reliability Evaluation)

  • 하경재;김원경
    • 한국시뮬레이션학회논문지
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    • 제10권2호
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    • pp.61-74
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    • 2001
  • The reliability evaluation of the large scale network becomes very complicate according to the growing size of network. Moreover if the reliability is not constant but follows probability distribution function, it is almost impossible to compute them in theory. This paper studies the network evaluation methods in order to overcome such difficulties. For this an efficient path set algorithm which seeks the path set connecting the start and terminal nodes efficiently is developed. Also, various variance reduction techniques are applied to compute the system reliability to enhance the simulation performance. As a numerical example, a large scale network is given. The comparisons of the path set algorithm and the variance reduction techniques are discussed.

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RLP : An Efficient HSR Traffic Reduction Algorithm

  • ;전제현;신상헌;이종명
    • 한국위성정보통신학회논문지
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    • 제7권3호
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    • pp.47-53
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    • 2012
  • In this paper, we present an algorithm called redundant logical paths (RLP) for efficient HSR traffic reduction. It creates redundant logical paths between each HSR node and all the other nodes. Eventually, a logical full-meshed network or paths will be established among all HSR node types, except the Quadbox type, which is used only for interconnection. The logical full-meshed network will be used instead of using the standard HSR protocol that depends on the concepts of the duplication and forwarding of the received frame until it reaches the destination node. The RLP algorithm results in significantly less frame traffic because there is no random forwarding as in the standard HSR protocol. For the sample network in this paper simulation results showed a 61.5-80% reduction in network frame traffic compared to the standard HSR. Our algorithm will avoid latency issues in the network and even network congestion, thus improving network efficiency.

시간지연 신경회로망을 이용한 잡음제거 시스템 (Noise reduction system using time-delay neural network)

  • 최재승
    • 대한전자공학회논문지SP
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    • 제42권3호
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    • pp.121-128
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    • 2005
  • 음성신호를 대상으로 하는 연구 분야에서 신경회로망은 주로 음성인식 등의 카테고리 분류의 목적으로 사용되며 신호처리의 응용에도 유망하다. 따라서 본 논문에서는 신경회로망에 시간구조를 취한 시간지연 신경회로망을 이용하여 잡음이 중첩된 음성신호의 공간으로부터 잡음이 없는 음성신호의 공간으로 사상을 실행함으로써 잡음을 제거하는 것을 목적으로 한다. 본 논문은 푸리에 변환의 진폭성분을 복원하는 잡음제거의 알고리즘을 사용하여 백색잡음 및 유색잡음에 대해서 본 수법의 유효성을 확인한다.

RBF Neural Network Based SLM Peak-to-Average Power Ratio Reduction in OFDM Systems

  • Sohn, In-Soo
    • ETRI Journal
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    • 제29권3호
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    • pp.402-404
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    • 2007
  • One of the major disadvantages of the orthogonal frequency division multiplexing system is high peak-to-average power ratio (PAPR). Selected mapping (SLM) is an efficient distortionless PAPR reduction scheme which selects the minimum PAPR sequence from a group of independent phase rotated sequences. However, the SLM requires explicit side information and a large number of IFFT operations. In this letter we investigate a novel PAPR reduction method based on the radial basis function network and SLM.

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망축소작도법에 의한 대형회로망 전류원 처리 (Current Source Disposition of Large-scale Network with Loop-reduction Drawing Technique)

  • 황재호
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권5호
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    • pp.278-286
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    • 2000
  • A new large-scale network geometric analysis is introduced. For a large-scale circuit, it must be analyzed with a geometric diagram and figure. So many equations are induced from a geometric loop-node diagram. The results are arranged into a simple matrix, of course. In case of constructing a network diagram, it is not easy to handle voltage and current sources together. Geometric loop analysis is related to voltage sources, and node analysis is to current sources. The reciprocal transfer is possible only to have series or parallel impedance. If not having this impedance, in order to obtain equivalent circuit, many equations must be derived. In this paper a loop-reduction method is proposed. With this method current source branch is included into the other branch, and disappears in circuit diagram. So the number of independent circuit equations are reduced as much as that of current sources. The number is not (b-n+1), but (b-n+1-p). Where p is the number of current sources. The reduction procedure is verified with a geometric principle and circuit theory. A resultant matrix can be constructed directly from this diagram structure, not deriving circuit equations. We will obtain the last results with the help of a computer.

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