• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.6
• /
• pp.114-123
• /
• 1985

This is the second part of the four-part paper describing the development of a packet-switched computer network named the cORNET In this paper, following the first par paper that describes the concepts of the KORNET and the development of the network management center (NMC), wc present the design of the KORNET and the development of the network node processor (NNP) The initial configuration of the KORNET consists of three NNP's and one NMC. We have developed each NNP as a microprocessor-based (Mc68000) multiprocessor system, and implemented the NMC using a super-mini computer (Mv/8000) For the KORNET we use the virtual circuit (VC) method as the packet service strategy and the distributed adaptive routing algorithm to adapt efficiently the variation of node and link status. Also, we use a dynamic buffer management algorithm for efficient storage management. Thc hardware of the NNP system has been designed with emphasis on modularity so that it may be expanded esily . Also, the software of the NNP system has been developed according to the CCITT recommendations X.25, X.3, X.28 and X.29.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3144-3153
• /
• 1996

ATM switching system is made up of transport network and control newrk according to its functions. The control device, basic part of control network must be developed before developing any other functions, and control device must be stable and need high reliability. Out distributed ATM switching system consists of several ALSs that provides variable local call services, and an ACS that interconnect among several ALSs. Eech ALS has CCCP that takes charage of call and connection control functions, and ACS has an OMP that takes charge of OA&M(Operation, Administration and Maintenance) functios. In this paper, we analyzed the performance evaluation of control device that manipulate subscriber's call based on ITU-T Q.2931 standard protocol messages and Interprocessor communication messages. As a result of simulation when the number of ALS is under 22, as the call arrival rate increase the processor utilization of CCCP increase rapidly than that of OMP. When the number of ALS is incremented to 22, the processor utilization of CCCP is balanced with the of OMP, and when the number of ALS exceeds 22, the processor utiliztion of OMP increase rapidly. Also if messary processing time of OMP is 1.35 times that of CCCP, processor utilizations of CCCP and OMP is equal.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.46-49
• /
• 2011

This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.15 no.2
• /
• pp.224-229
• /
• 2005

Generally, genetic algorithm (GA) has too much time and space complexity when it is running in the typical processor. Therefore, we are forced to use the high-performance and expensive processor by this reason. It also works as a barrier to implement real device, such a small mobile robot, which is required only simple rules. To solve this problem, this paper presents and proposes enhanced processor-architecture for the faster GA processing. A typical processor architecture can be enhanced and specialized by two approaches: one is a sorting network, the other is a residue number system (RNS). A sorting network can improve the time complexity of which needs to compare the populations' fitness. An RNS can reduce the magnitude of the largest bit that dictates the speed of arithmetic operation. Consequently, it can make the total logic size smaller and innovate arithmetic operation speed faster.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.313-316
• /
• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• International journal of advanced smart convergence
• /
• v.11 no.1
• /
• pp.28-35
• /
• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.1-7
• /
• 1996

In this paper, we analyzed the packet blocking probability of a finite buffer in a network interface unit. In general, a network interface unit which provides a means of interface between the network and computer has a microprocessor and a protocol processor for the network access protocols. It also has a receive buffer for the arriving packets from the network which is served by the microprocessor with service interruption by the protocol processor. In this paper, we modeled the receive buffer as a discrete time server with service interruption, and obtained the packet blocking probability using the mini-slot approximation.

• Journal of IKEEE
• /
• v.21 no.1
• /
• pp.92-95
• /
• 2017

In this paper, we proposed a way to improve function of small scale GP-GPU. Instead of using superscalar which increase scheduling-complexity, we suggested the application of simple core to maximize GP-GPU performance. Our studies also demonstrated that simplified Stream Processor is one of the way to achieve functional improvement in GP-GPU. In addition, we found that developing of optimal thread-assigning method in Warp Scheduler for specific application improves functional performance of GP-GPU. For examination of GP-GPU functional performance, we suggested the thread-assigning way which coordinated with Deep-Learning system; a part of Neural Network. As a result, we found that functional index in algorithm of Neural Network was increased to 90%, 98% compared with Intel CPU and ARM cortex-A15 4 core respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 1996.11a
• /
• pp.738-742
• /
• 1996

This paper presents the automatic monitoring system for the small and medium sized manufacturing system. The monitoring system was composed of main controller, network card and monitoring sub controller for the unit machine. PC was used for the main controller and monitoring controller, which has the same hardware with the network card, was developed using Intel 80196 microprocessor.

• Proceedings of the KAIS Fall Conference
• /
• 2008.11a
• /
• pp.191-196
• /
• 2008

The intent of this paper is to describe a neural network structure called dynamic neural processor(DNP), and examine how it can be used in developing a learning scheme for computing robot inverse kinematic transformations. The architecture and learning algorithm of the proposed dynamic neural network structure, the DNP, are described. Computer simulations are provided to demonstrate the effectiveness of the proposed learning using the DNP.