• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• Korean Journal of Ichthyology
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• v.35 no.4
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• pp.224-235
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• 2023

South Korea is the only divided nation globally, marked by a military demarcation line establishing demilitarized and civilian control zones, ensuring national security. Consequently, these areas exhibit relatively minimal ecological disruption compared to other regions. However, the threat to safety persists due to the presence of unexploded ordnances and landmines, imposing significant constraints on ecological research. To address this, we conducted a comparative study utilizing eDNA analysis as a supplementary and alternative approach within three points of the "Road of Peace" - Inje, Yanggu, and Hwacheon courses, located within the civilian control zone. Direct surveys and indirect eDNA sampling were carried out in May, July, and September of 2022. Genetic material obtained from the samples underwent amplification, library preparation, MiSeq sequencing, and subsequent ASV generation for indirect analysis. These results were then compared with the findings of direct surveys. Our findings revealed the detection of eDNA for both observed species at the Yanggu-1 point, and for two out of four species at Yanggu-2. Hwacheon-1 displayed the detection of eDNA for one out of one observed species, whereas Hwacheon-2 yielded seven out of twelve, Hwacheon-3 showed four out of six, and all one observed species at Hwacheon-4 exhibited eDNA detection. Consequently, approximately 69% of the fish species identified through direct surveys were confirmed by indirect eDNA analysis. It is necessary to verify if certain fish species, such as the continental trout and catfish, have genetic information registered in the NCBI database. Additionally, it is believed that further marker development research utilizing different genetic sequences is essential. Given the limitations imposed by the hazardous nature of the surveyed civilian control zone, eDNA analysis proves to be a suitable supplement for fish research in the area.

• Journal of the Korean Society for information Management
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• v.25 no.4
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• pp.5-23
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• 2008

The National Library of Korea is administering a legal deposit system for the printedpublications. Whereas, OASIS(Online Archiving & Searching Internet Sources) has to design a system to collect, manage and preserve web sites and web resources for Web Archiving. The purpose of this study is to develop a digital deposit process for digital resources. As a result, this study defines the subjects and objects for digital deposits, and describes the definitions and the functions according to digital deposit steps. Also, this study designs the data flow diagram and proposes the function definitions on unit works and the structure for the flow of information.

• Korean Journal of Optics and Photonics
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• v.17 no.5
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• pp.391-395
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• 2006

In this paper, radiometric calibration of a FTIR spectrometer for passive remote sensing application was introduced and verified. Radiometric calibration is a significant signal processing procedure to retrieve the object radiance from the measured spectrum. The object radiance is measured and registered distorted by the detector's responsivity dependent on wavelength and instrument self-emission. Radiance of two temperature points, hot temperature and cold temperature, from a well-controlled blackbody was measured and used to obtain the scale factor and offset factor which are required for radiometric calibration. For gas phase C2H5OH. radiometric calibration was done and verified through comparison of its emission line width and intensity with the standard spectrum.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Spatial Information Research
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• v.22 no.2
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• pp.63-71
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• 2014

Ocean leisure sports have recently emerged as one of so-called blue ocean industries. They are sensitive to diverse environmental conditions such as current, temperature, and salinity, which can increase needs of forecasting data as well as in-situ observations for the ocean. In this context, a Web-based geovisualization system for coastal information produced by model forecasts was implemented for use in supporting various ocean activities. First, FVCOM(Finite Volume Coastal Ocean Model) was selected as a forecasting model, and its data was preprocessed by a spatial interpolation and sampling library. The interpolated raster data for water surface elevation, temperature, and salinity were stored in image files, and the vector data for currents including speed and direction were imported into a distributed DBMS(Database Management System). Web services in REST(Representational State Transfer) API(Application Programming Interface) were composed using Spring Framework and integrated with desktop and mobile applications developed on the basis of hybrid structure, which can realize a cross-platform environment for geovisualization.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1419-1432
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• 1999

The Document Management System(DMS) is a system which retrieves and manages library information efficiently. Since DMS manages the information using only one table, it does not need to provide join and view operations that spend high cost in traditional DBMS. In addition, DMs requires new operations because of their property. the operation has not been supported in existing DBMSs. In this paper we define a data language which represents the structure definition and process of data on the DMS. Especially we define Ranking and Proximity operation which is needed in Document Retrieval,. We also design and implement a query processor to process the query constructed with the data language. When the exiting query processors of relational DBMS are used as a query processor of DMS, they degrade the whole system performance. The proposed query processor not only overcomes such a problem but also supports new operation which is needed in DMS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.78-83
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• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.