• Applied Science and Convergence Technology
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• v.23 no.2
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• pp.61-71
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• 2014

A field-effect transistor (FET) is one of the most commonly used semiconductor devices. Recently, increasing interest has been given to FET-based biosensors owing totheir outstanding benefits, which are likely to include a greater signal-to-noise ratio (SNR), fast measurement capabilities, and compact or portable instrumentation. Thus far, a number of FET-based biosensors have been developed to study biomolecular interactions, which are the key drivers of biological responses in in vitro or in vivo systems. In this review, the detection principles and characteristics of FET devices are described. In addition, biological applications of FET-type biosensors and the Debye length limitation are discussed.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.259-265
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• 2009

We fabricated the field effect transistor using single crystalline ZnO nanowires synthesized by a conventional thermal evaporation method and investigated their basic properties under the various conditions such as ultraviolet irradiation, reducing gas and electrolyte. The typical carrier concentration and mobility of the single crystalline ZnO nanowire with a diameter of 100 nm and length of 5 um were $1.30{\times}10^{18}cm^{-3}$ and $15.6cm^2V^{-1}s^{-1}$, respectively. The current of ZnO nanowire under ultraviolet irradiation significantly increased about 400 times higher as compared to in the darkness. In addition, the ZnO nanowire showed typical sensing characteristics for $H_2$ and CO due to well-known surface reactions and typical current-voltage characteristics under the 0.1 M NaCl electrolyte.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.123-123
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• 2008

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• Journal of the Korean institute of surface engineering
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• v.41 no.1
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• pp.12-15
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• 2008

The zinc oxide(ZnO) nanowires were deposited on Si(001) substrates by thermal chemical vapour deposition without any catalysts. SEM data suggested that the grown nanostructures were the well-aligned ZnO single crystals with preferential orientation. Back-gate ZnO nanowire field effect transistors(FET) were successfully fabricated using a photolithography process. The fabricated nanowire FET exhibits good contact between the ZnO nonowire and Au metal electrodes. Based on I-V characteristics it was found out that the ZnO nanowire revealed a characteristic of n-type field effect transistor. The drain current increases with increasing drain voltage, and the slopes of the $I_{ds}-V_{ds}$ curves are dependent on the gate voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.432-432
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• 2009

본 연구에서는 HW-PLD(Hot-walled Pulsed Laser Deposition) 법을 이용하여 ZnO 나노와이어를 $Al_2O_3$ 기판 위에 성장하였다. 성장된 ZnO 나노와이어는 SEM, XRD, PL 분석을 통하여 구조적 특성을 확인하였으며, 성장된 나노와이어를 photolithography 공정을 통하여 FET(Field Effect Transistor)소자를 제작하였다. 제작된 소자의 I-V 특성 측정 결과 Ti/Au 전극과 ZnO nanowire 채널 간에 ohmic 접합이 형성된 것을 확인하였으며 게이트 전압의 증가에 따라 소스와 드레인 사이의 전류가 증가하는 전형적인 n-type FET소자 특성을 나타내었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1005-1009
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• 2006

High quality three-dimensional (3D) heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate to improve the efficiency of tarrier transport. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources (As2, As4) were varied to calibrate the selective area growth conditions and the 3D GaAs-AlGaAs heterostructures were fabricated into the ridge type and the V-groove type. Scanning micro-photoluminescence $({\mu}-PL)$ measurements and the following analysis revealed that the gradually (adiabatically) coupled 1D-2DEG (electron gas) field effect transistor (FET) system was successfully realized. These 3D-heterostructures are expected to be useful for the realization of high-performance mesoscopic electronic devices and circuits since it makes it possible to form direct ohmic contact onto the (quasi) 1D electron channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.167-168
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• 2006

High quality 3D-heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources ($As_2$, $As_4$) were varied to calibrate the selective area growth conditions. Scanning micro-photoluminescence ($\mu$-PL) measurements and following analysis revealed that the gradually (adiabatically) coupled 2DEG-1D-1DEG field effect transistor (FET) system was realized. This 3D-heterostructure is very promising for the realization of the meso-scopic electronic devices and circuits since it makes it possible to form direct ohmic contact to the (quasi) 1DEG.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.132-132
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• 2009

A 2D-simulation using a quantum model of silicon nanowire (SiNW) field-effect transistors (FETs) have been performed by the effective mass theory. We have investigated very close for real device analysis, so we used to the non-equilibrium Green's function (NEGF) and the density gradient of quantum model. We investigated I-V characteristics curve and C-V characteristics curve of the channel thickness from 5nm to 200nm. As a result of simulation, even higher drain current in SiNW using a quantum model was observed than in SiNW using a non-quantum model. The reason of higher drain current can be explained by the quantum confinement effect.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.