• Vacuum Magazine
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• v.3 no.3
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• pp.10-14
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• 2016

Semiconductor nanowires (NWs) refer to one-dimensional semiconductor materials that have a diameter constrained to tens of nanometers or less and an unconstrained length. Over the past few decades, most efforts in the semiconductor NWs have been focused on synthesis, structure and morphology control, and assembly, as appropriate for diverse functional device applications. This paper provides a detailed overview of the recent research activities and major achievements in nanowire research, which especially includes nanowires synthesis, position and direction-controlled assembly or growth. In addition, the fine tuning of structure and morphology, and the related properties and device applications of the NWs are highlighted.

• Korean Journal of Materials Research
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• v.32 no.8
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• pp.333-338
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• 2022

In this work, we developed silver nanowires and a silicon based Schottky junction and demonstrated ultrafast broadband photosensing behavior. The current device had a response speed that was ultrafast, with a rising time of 36 ㎲ and a falling time of 382 ㎲, and it had a high level of repeatability across a broad spectrum of wavelengths (λ = 365 to 940 nm). Furthermore, it exhibited excellent responsivity of 60 mA/W and a significant detectivity of 3.5 × 10¹² Jones at a λ = 940 nm with an intensity of 0.2 mW cm^-2 under zero bias operating voltage, which reflects a boost of 50 %, by using the AC PV effect. This excellent broadband performance was caused by the photon-induced alternative photocurrent effect, which changed the way the optoelectronics work. This innovative approach will open a second door to the potential design of a broadband ultrafast device for use in cutting-edge optoelectronics.

• Journal of Powder Materials
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• v.16 no.2
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• pp.138-145
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• 2009

The combination of focused ion beam (FIB) and 4 point probe nanomanipulator could make various nano manufacturing and electrical measurements possible. In this study, we manufactured individual ZnO nanowire devices and measured those electrical properties. In addition, tensile experiments of metallic Au and Pd nanowires was performed by the same directional alignment of two nanomanipulators and a nanowire. It was confirmed from I-V curves that Ohmic contact is formed between electrodes and nanomanipulators, which is able to directly measure the electrical properties of a nanowire itself. In the mechanical tensile test, Au and Pd nanowires showed a totally different fracture behavior except the realignment from <110> to <002>. The deformation until the fracture was governed by twin for Au and by slip for Pd nanowires, respectively. The crystallographic relationship and fracture mechanism was discussed by TEM observations.

• Proceedings of the Korean Magnestics Society Conference
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• 2010.06a
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• pp.79-79
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• 2010

Semimetallic bismuth (Bi) has been extensively investigated over the last decade since it exhibits very intriguing transport properties due to their highly anisotropic Fermi surface, low carrier concentration, long carrier mean free path l, and small effective carrier mass $m^*$. In particular, the great interest in Bi nanowires lies in the development of nanowire fabrication methods and the opportunity for exploring novel low-dimensional phenomena as well as practical application such as thermoelectricity[1]. In this work, we introduce a self-assembled interconnection of nanostructures produced by an on-film formation of nanowires (OFF-ON) method in order to form a highly ohmic Bi nanobridge. A Bi thin film was first deposited on a thermally oxidized Si (100) substrate at a rate of $40\;{\AA}/s$ by radio frequency (RF) sputtering at 300 K. The sputter system was kept in an ultra high vacuum (UHV) of $10^{-6}$ Torr before deposition, and sputtering was performed under an Ar gas pressure of 2m Torr for 180s. For the lateral growth of Bi nanowires, we sputtered a thin Cr (or $SiO_2$) layer on top of the Bi film. The Bi thin films were subsequently put into a custom-made vacuum furnace for thermal annealing to grow Bi nanowires by the OFF-ON method. After thermal annealing, the Bi nanowires cannot be pushed out from the topside of the Bi films due to the Cr (or $SiO_2$) layer. Instead, Bi nanowires grow laterally as a mean s of releasing the compressive stress. We fabricated a self-assembled Bi nanobridge (d=192 nm) device in-situ using OFF-ON through annealing at $250^{\circ}C$ for 10hours. From I-V measurements taken on the Bi nanobridge device, contacts to the nanobridge were found highly ohmic. The quality of the Bi nanobridge was also proved by the high MR of 123% obtained from transverse MR measurements. These results manifest the possibility of self-assembled nanowire interconnection between various nanostructures for a variety of applications and provide a simple device fabrication method to investigate transport properties on nanowires without complex patterning and etching processes.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.5
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• pp.368-374
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• 2016

This paper presents an experimental study on an electrical circuit model of the TiO2-based nano-wired memristor device for neuromophic applications. The electrical circuit equivalent model of the proposed memristor device consists of several electronics components and some passive devices including operational amplifiers, multipliers, resistors and capacitors. In order to verify the proposed design, both of simulation (using PSPICE) as well as hardware implementation were performed for the analysis of the memristor circuit with time waveforms, frequency spectra, I-V curves and power curves. The gained results from the measured data showed a good agreement with the simulation result that confirm the proposed idea.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.198-198
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• 2012

Graphene has been the subject of intense study in recent years owing to its good optoelectronic properties, possibility for stretchable electronics, and so on. Especially, many research groups have studied about graphene nanostructures with various sizes and shapes. Graphene needs to be fabricated into useful devices with controllable electrical properties for its successful device applications. However, this been far from satisfaction owing to a lack of reliable pattern transfer techniques. Photolithography, nanowire etching, and electron beam lithography methods are commonly used for construction of graphene patterns, but those techniques have limitations for getting controllable GNRs. We have developed a novel nanoscale pattern transfer technique based on an electro-hydrodynamic lithography providing highly scalable versatile pattern transfer technique viable for industrial applications. This technique was exploited to fabricate nanoscale patterned graphene structures in a predetermined shape on a substrate. FE-SEM, AFM, and Raman microscopy were used to characterize the patterned graphene structures. This technique may present a very reliable high resolution pattern transfer technique suitable for graphene device applications and can be extended to other inorganic materials.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Journal of Electrochemical Science and Technology
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• v.3 no.2
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• pp.68-71
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• 2012

The electrospinning technique is a revolutionary template-catalyst-free method that can generate 1D nanostructure with the tunability and the potential for the mass production. This approach received a great deal of attention due to its ability to give direct pathways for electrical current and has been utilized in various electronic applications. However, the delamination of inorganic electrospun film has prevented the intense utilization due to the thermal expansion/contraction during the calcination. In this study, we propose an electrical grounding method for transparent conducting oxide and electrospun nanowires to enhance the adhesion after the calcination. Then, we examined the potential of the technique on ZnO based dye-sensitized solar cells.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.1-9
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• 2006

We introduce our in-house program, NANOCAD, for the modeling and simulation of carrier transport in nanoscale MOSFET devices including quantum-mechanical effects, which implements two kinds of modeling approaches: the top-down approach based on the macroscopic quantum correction model and the bottom-up approach based on the microscopic non-equilibrium Green’s function formalism. We briefly review these two approaches and show their applications to the nanoscale bulk MOSFET device and silicon nanowire transistor, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.60-60
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• 2010

최근 사람의 피부나 내부 장기처럼 수축과 팽창이 일어나는 부위 등에 이식 가능한 소자 개발에 대한 연구가 많이 보고되었다. 현재 이런 stretchable electronics에 대한 연구는 channel material로서 실리콘이나 유기물, 그리고, 광학 리소그래피가 가능한 micro-electronics 에 국한되어 있다. 우리는 CVD 로 성장된 수십 나노미터의 직경을 갖는 $SnO_2$ 나노선을 슬라이딩 전이하여 실리콘 웨이퍼 상에서 소자화하고 이를 스트레칭이 가능한 PDMS 기판에 전이하여 stretchable nanowire device를 구현하였다. 해당 소자는 윗면과 아랫면 모두 폴리머로 덮여 있고 측정을 위한 전극이 따로 구성되어 있어 소자 특성의 열화가 최소화되게 제작되었으며, 수축과 팽창 시 받는 스트레인 또한 최소화하는 mechanical neutral structure를 갖게 제작되었다. 또한, 소자와 소자 혹은 소자와 전극간의 연결을 S자 형태로 구성하여 기판으로 사용된 PDMS를 수십 % 스트레칭하여도 소자의 전기적 특성이 유지되는 것을 확인하였다. 이처럼 스트레칭이 가능한 나노선 소자는 구김이나 잡아 늘여지게 되는 다양한 표면위에 간단하게는 논리회로뿐만 아니라 나노선의 장점을 이용한 다양한 센서 및 기능 소자로서 응용이 가능할 것으로 예상된다.