• 제목/요약/키워드: Nano-Electronics

검색결과 742건 처리시간 0.037초

완전 결핍 SOI MOSFET의 계면 트랩 밀도에 대한 급속 열처리 효과 (Effect of rapid thermal annealing on interface trap density by using subthreshold slope technique in the FD SOI MOSFETs)

  • Jihun Oh;Cho, Won-ju;Yang, Jong-Heon;Kiju Im;Baek, In-Bok;Ahn, Chang-Geun;Lee, Seongjae
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.711-714
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    • 2003
  • In this presentation, we investigated the abnormal subthreshold slope of the FD SOI MOSFETs upon the rapid thermal annealing. Based on subthreshold technique and C-V measurement, we deduced that the hump of the subthreshold slope comes from the abnormal D$_{it}$ distribution after RTA. The local kink in the interface trap density distribution by RTA drastically degrades the subthreshold characteristics and mini hump can be eliminated by S-PGA.A.

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Enhancement of Dielectric Properties of Polyamide Enamel Insulation in High Voltage Apparatuses Used in Medical Electronics by Adding Nano Composites of SiO2 and Al2O3 Fillers

  • Biju, A.C.;Victoire, T. Aruldoss Albert;Selvaraj, D. Edison
    • Journal of Electrical Engineering and Technology
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    • 제10권4호
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    • pp.1712-1719
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    • 2015
  • In recent days, there was a significant development on the electrical, thermal, mechanical, physical, chemical, magnetic and optical properties of the polyamide enamel, varnish and other insulating materials by the addition of nano fillers to it. Enamel was used in High Voltage Apparatuses used in Medical Electronics as insulation. Insulating materials determine the life time of the electrical apparatuses. The life time of the insulating materials was improved by the addition of nano fillers to it. Hence the life time of the electrical apparatuses was improved by the mixing of nano fillers to the enamel. In this research, the basic dielectric properties of the enamel and enamel mixed with nano composites of silica and alumina were analyzed and compared with each other. The addition of nano fillers has improved the quality factor and capacitance of the enamel. It was also observed that the addition of nano fillers has reduced the dissipation factor and dielectric losses of the enamel. Heat produced by the dielectric losses was also reduced by adding nano fillers to it.

Schottky Barrier MOSFETs with High Current Drivability for Nano-regime Applications

  • Jang, Moon-Gyu;Kim, Yark-Yeon;Jun, Myung-Sim;Choi, Chel-Jong;Kim, Tae-Youb;Park, Byoung-Chul;Lee, Seong-Jae
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권1호
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    • pp.10-15
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    • 2006
  • Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from $20{\mu}m$ to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed $550{\mu}A/um$ saturation current at $V_{GS}-V_T$ = $V_{DS}$ = 2V condition ($T_{ox}$ = 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.

Erbium 실리사이드를 이용하여 제작한 n-형 쇼트키장벽 관통트랜지스터의 전기적 특성 (Characteristics of Erbium silicided n-type Schottky barrier tunnel transistors)

  • Moongyu Jang;Kicheon Kang;Sunglyul Maeng;Wonju Cho;Lee, Seongjae;Park, Kyoungwan
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.779-782
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    • 2003
  • The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics.

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RIE 공정을 이용한 유기발광다이오드의 광 산란층 제작 (Fabrication of Scattering Layer for Light Extraction Efficiency of OLEDs)

  • 배은정;장은비;최근수;서가은;장승미;박영욱
    • 반도체디스플레이기술학회지
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    • 제21권1호
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    • pp.95-102
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    • 2022
  • Since the organic light-emitting diodes (OLEDs) have been widely investigated as next-generation displays, it has been successfully commercialized as a flexible and rollable display. However, there is still wide room and demand to improve the device characteristics such as power efficiency and lifetime. To solve this issue, there has been a wide research effort, and among them, the internal and the external light extraction techniques have been attracted in this research field by its fascinating characteristic of material independence. In this study, a micro-nano composite structured external light extraction layer was demonstrated. A reactive ion etching (RIE) process was performed on the surfaces of hexagonally packed hemisphere micro-lens array (MLA) and randomly distributed sphere diffusing films to form micro-nano composite structures. Random nanostructures of different sizes were fabricated by controlling the processing time of the O2 / CHF3 plasma. The fabricated device using a micro-nano composite external light extraction layer showed 1.38X improved external quantum efficiency compared to the reference device. The results prove that the external light extraction efficiency is improved by applying the micro-nano composite structure on conventional MLA fabricated through a simple process.

PZT 캔틸레버 구동기와 마이크로 시소구조를 적용한 저전압 SPDT MEMS RF 스위치 구현 (Implementation of a Low Actuation Voltage SPDT MEMS RF Switch Applied PZT Cantilever Actuator and Micro Seesaw Structure)

  • 이대성;김원효;정석원;조남규;성우경;박효덕
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.147-150
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    • 2005
  • Low actuation voltage and no contact stiction are the important factors to apply MEMS RF switches to mobile devices. Conventional electrostatic MEMS RF switches require several tens of voltages for actuation. In this paper we propose PAS MEMS RF switch which adopt PZT actuators and seesaw cantilevers to meet the above requirements. The fundamental structures of PAS MEMS switch were designed, optimized, and fabricated. Through the developed processes PAS SPDT MEMS RF switches were successfully fabricated on 4" wafers and they showed good electrical properties. The driving voltage was less than 5 volts. And the insertion loss was -0.5dB and the isolation was 35dB at 5GHz. The switching speed was about 5kHz. So these MEMS RF switches can be applicable to mobile communication devices or wireless multi-media devices at lower than 6GHz.

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Effects of Oxidation on the Order-disorder Transition in NiPt Alloy Nano Crystals

  • 서옥균;황재성;송다현;이지연;최정원;이수웅;강현철;노도영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.253-253
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    • 2012
  • The effects of oxidation on the order-disorder transition in NiPt bimetallic alloy crystal have been investigated using in-situ synchrotron x-ray scattering technique. The temperature dependence of the crystal structure and the order parameter were measured during in-situ heating and cooling under vacuum and oxygen environments. The order-disorder transition temperature of NiPt alloy crystals in vacuum was between $615^{\circ}C$ and $627^{\circ}C$. On the other hand under oxygen environment, the transition temperature decreases by about $31^{\circ}C$ after the oxidation. The change of the transition temperature can be explained by the formation of NiO crust on the surface of NiPt crystal, which alters the composition of the Ni and Pt atoms. Since the transition temperature depends sensitively on the Ni-Pt composition, the transition temperature changes as Ni atoms diffuse out to form NiO.

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Packaging 형태에 따른 CMOS ISFET pH 센서의 특성평가 (Characteristics of CMOS ISFET pH sensor as packaging type)

  • 신규식;노지형;조남규;이대성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.517-518
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    • 2008
  • Highly integrated ISFETs require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip This paper presents novel packaging type of CMOS ISFET pH sensor using standard CMOS FET chip and extended sensing membrane which is separated from CMOS FET. This proposed packaging type will make it easy to fabricate CMOS ISFET pH sensors

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Nano-porous $Al_2O_3$ used as a protecting layer of AC Plasma Display Panel

  • Park, Sung-Yun;Hong, Sang-Min;Shin, Bhum-Jae;Cho, Jin-Hoon;Kim, Seong-Su;Park, Sung-Jin;Lee, Kyu-Wang;Choi, Kyung-Cheol
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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    • pp.359-361
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    • 2003
  • Nano-porous alumina was investigated as a protecting layer in an AC Plasma Display Panel. A 2 ${\mu}m$ thick nano-porous $Al_2O_3$ layer inserted with MgO was formed on the dielectric layer instead of the conventional 500 nm-thick MgO thin film. Both nano-porous $Al_2O_3$layer and inserted MgO were prepared by wet process. The luminance and luminous efficiency of 3-inch test panel adopting nano-porous $Al_2O_3$ was higher than that of the conventional PDP.

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An Reliable Non-Volatile Memory using Alloy Nano-Dots Layer with Extremely High Density

  • Lee, Gae-Hun;Kil, Gyu-Hyun;An, Ho-Joong;Song, Yun-Heup
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.241-241
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    • 2010
  • New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.

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