• Journal of Computing Science and Engineering
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• v.9 no.4
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• pp.177-189
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• 2015

High-performance processors using Non-Uniform Cache Architecture (NUCA) are increasingly used to deal with the growing wire delays in multicore/manycore processors. Due to the convergence of high-performance computing with embedded computing, NUCA caches are expected to benefit high-end embedded systems as well. However, for real-time systems that use multicore processors with NUCA caches, it is crucial to bound worst-case execution time (WCET) accurately and safely. In this paper, we developed a WCET analysis approach by considering the effect of static NUCA caches on WCET. We compared the WCET in real-time applications with different topologies of static NUCA caches. Our experimental results demonstrated that the static NUCA cache could improve the worst-case performance of realtime applications using multicore processor compared to the cache with uniform access time.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.20 no.3
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• pp.353-364
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• 2007

In this paper, a nonlinear finite element analysis program NUCAS, which has been developed for assessment of ultimate pressure capacity and failure mode for nuclear containment building is described. Degenerated shell element with assumed strain method and low-order solid element with enhanced assumed strain method is adapted to microscopic material and elasto-plastic material model, respectively. Finally, the performance of the developed program is tested and demonstrated with several examples. From the numerical tests, the present results show a good agreement with experimental data or other numerical results.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.13-21
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• 2013

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.